Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification
In this presentation, we will introduce Questa Verify Trust and discuss some experiences and initial results from two projects at Lockheed Martin. An objective is to verify the incoming IPs for Trust, as incoming 3rd party RTL IPs may introduce security-relevant weaknesses and vulnerabilities. Another project must complete Trust Verification as a critical step of the Defense Microelectronics Activity (DMEA) trusted flow.
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