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Back to the Future with Formal Property Checking (PDF)
Resource - Apr 03, 2023 by
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The Digital Twin: An Aerospace and Defense Revolution
Session - Mar 29, 2023 by Ray Salemi
This session will provide a look into a seamless and comprehensive Digital Thread for Defense and the immense value it brings.
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Continuous Integration (CI) driving efficient program execution
Webinar - Mar 28, 2023 by Kevin Campbell
In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
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Continuous Integration (CI) driving efficient program execution
Resource (Slides) - Mar 28, 2023 by Kevin Campbell
In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
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How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Webinar - Mar 18, 2023 by Joon Hong
In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.
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Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Webinar - Mar 16, 2023 by Neil Johnson
In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.
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Introduction to SystemVerilog Assertions
Webinar - Mar 15, 2023 by Chris Crile
In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.
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Rapid Testbench Development
Resource (Slides) - Mar 07, 2023 by Bob Oden
Slides covering the UVM Framework, system model refinement and automated testbench creation.
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Big Data Reimagines Verification Predictability and Efficiency
Article - Feb 24, 2023 by Darron May
Big data is a term that has been around for many years. The list of applications for big data is endless, but the process stays the same: capture, process, and analyze. With new, enabling verification solutions, big data technologies can improve your verification process efficiency and predict your next chip sign-off.
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Democratizing Digital-Centric Mixed-Signal Verification Methodologies
Article - Feb 24, 2023 by Sumit Vishwakarma
As the world of technology continues to evolve, the way we design and verify circuits is also evolving. The next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern System-on-Chips (SoCs). Mixed-signal designs are a combination of tightly interwoven analog and digital circuitry. There are two main reasons for increased mixed-signal contents in today's SoC.
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Lane Margining at Receiver and its Application Through Pipe Message Bus
Article - Feb 24, 2023 by Sachin Mishra
PCI Express® (PCIe) announced its fourth generation (PCIe 4.0 standard) in year 2017.With PCIe Gen 3 the speed of operation was 8 GT/s (giga transfers per second) and error rate is manageable (10-12) but with doubling the frequency with each successive generations performance degradation become more pronounced due to variety of reasons like losses in the channels due to different components, reflections in the channel, jitter and cross talk between lanes in a multi-lane system.
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The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines
Article - Feb 24, 2023 by Aimee Sutton, Lee Moore, Kevin McDermott - Imperas Software
The open standard ISA of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor, right up to the state-of-the-art processor arrays with vector extensions for advanced AI applications and HPC.
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A Formal-based Approach for Efficient RISC-V Processor Verification
Article - Feb 24, 2023 by Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip
The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new functionality that inadvertently creates specification and design bugs.
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Jumpstart your Formal Verification with a Little Help
Article - Feb 24, 2023 by Doug Smith
An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis.
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Resolving Metastability Issues for Multi-clock SoC Environment for I2C
Article - Feb 24, 2023 by Priyanka Changan, Darshan Sarode, Avnita Pal, Priyanka Gharat - Silicon Interfaces
This article aims to resolve metastability issues for multi-clock designs by noting the clock domains and the synchronization required for crossing the clock domains. The example SoC has an 8-bit simple Microcontroller and a Memory Module with a clock differently aligned (multi-clock) to the I2C Master and Slave. Leading to issues regarding metastability that needed to be resolved using synchronizers – currently two flip-flops using a closed-loop solution for sending and receiving clock domains.
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Big Data for Verification – Inspiration from Large Language Models
Resource (Verification Horizons Blog) - Feb 24, 2023 by Dan Yu
ChatGPT, one of the most prominent Large Language Models (LLMs), has proven it is capable of human-level knowledge by passing multiple exams with faded colors: Warton’s MBA exam with a B, the US Medical Licensing Exam at the threshold, and four law school courses at the University of Minnesota with a C+. Individually, they are definitely not the best an excellent professional can achieve, but still are a good demonstration of LLMs’ strengths of appearing universally knowledgeable.
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Simulating UVMF Code on Windows
Session - Feb 20, 2023 by Graeme Jessiman
In this session, you will learn how to use the UVMF Build/Compile/Run script on Windows.
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Simulating UVMF Code on Windows
Resource (Slides) - Feb 20, 2023 by Graeme Jessiman
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Generating UVMF Code on Windows
Session - Feb 20, 2023 by Graeme Jessiman
In this session, you will learn how to use the generation scripts on Windows to produce UVMF testbench source.
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Generating UVMF Code on Windows
Resource (Slides) - Feb 20, 2023 by Graeme Jessiman
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Installing Python on Windows
Session - Feb 20, 2023 by Graeme Jessiman
In this session, you will learn how to install Python on a Windows system for use with UVMF scripts.
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Installing Python on Windows
Resource (Slides) - Feb 20, 2023 by Graeme Jessiman
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UVMF Build/Compile/Run Script Introduction
Session - Feb 20, 2023 by Jonathan Craft
In this session, you will be introduced to the capabilities and use of the UVMF Build/Compile/Run script.
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UVMF Build/Compile/Run Script
Resource (Slides) - Feb 20, 2023 by Jonathan Craft
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Register Adapters, Predictors, and Tests
Resource (Slides) - Feb 20, 2023 by Nick Galvan