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Register Adapters, Predictors and Tests
Session - Feb 20, 2023 by Nick Galvan
In this session, you will learn how to use register model adapters, predictors, and tests in UVMF.
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Register Model Generation and Replacement
Session - Feb 20, 2023 by Nick Galvan
In this session, you will learn how to produce a UVM register model, applying it to a UVMF testbench.
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Register Model Generation and Replacement
Resource (Slides) - Feb 20, 2023 by Nick Galvan
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Register Model Generation and Integration
Session - Feb 20, 2023 by Nick Galvan
In this session, you will be introduced to the generation of a register model as part of a UVMF environment.
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Register Model Generation and Integration
Resource (Slides) - Feb 20, 2023 by Nick Galvan
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UVM Framework Release 2023.1
Resource (Tarball) - Feb 20, 2023 by Bob Oden
General Updates: Added BASE_T type parameter to scoreboard classes to allow insertion of user base class. Added supper.xxx_phase calls to classes with BASE_T type parameter.
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UVM Framework
Track - Feb 20, 2023 by Bob Oden
In this track you will learn more about UVM Framework and how it that provides a reusable UVM methodology and code generator for rapid testbench generation.
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Verification Data Analytics with Machine Learning
Resource (Technical Paper) - Jan 25, 2023 by Dan Yu
This white paper provides an overview on the importance of data to ML, the available data for verification, and the existing applications of ML in verification. It reveals that data itself may dictate applicable ML models. Machine learning has demonstrated great potential in verification. However, attention should be paid to generalizing and scaling the models to ensure their success in a production environment.
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The UVM Factory Revealed - Part 2
Resource (Verification Horizons Blog) - Jan 25, 2023 by Chris Spear
This is a follow up to last week’s high-level post on the UVM Factory . Now let’s get technical! Here are the SystemVerilog Object-Oriented Programming concepts behind the factory.
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Epilogue: 2022 Study Summary and Key Findings
Resource (Verification Horizons Blog) - Jan 23, 2023 by Harry Foster
This is the last in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.
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FPGA Functional Verification Trend Report - 2022
Resource (Slides) - Jan 23, 2023 by Harry Foster
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IC/ASIC Functional Verification Trend Report - 2022
Resource (Slides) - Jan 23, 2023 by Harry Foster
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The UVM Factory Revealed - Part 1
Resource (Verification Horizons Blog) - Jan 20, 2023 by Chris Spear
When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming. Except one, the UVM Factory. Why do you need all that extra code, class::type_id::create(), just to make an object? What’s wrong with just calling new()? The answer is teamwork!
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Does Your UVM Flavor Have Sprinkles?
Resource (Verification Horizons Blog) - Jan 20, 2023 by Chris Spear
UVM is a standard, so that means that every company writes their testbenches the same, universally interchangeable, right? Not exactly. I just got back from teaching in Europe. No matter where the engineers grew up, they all spoke English, each with a different accent. I think that I don’t have an accent, having grown up in Alaska, but my coworkers in Texas and London would disagree. Let’s look at some of the different accents and flavors of UVM.
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Conclusion: Deeper Dive into Non-Trivial Bug Escapes
Resource (Verification Horizons Blog) - Jan 15, 2023 by Harry Foster
Our study results show that the IC/ASIC market has matured its verification processes overtime to address growing complexity, predominately driving by the emergence of SoC-class designs in the mid-2000 timeframe. Today we find the FPGA market is maturing its verification processes.
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Part 12: IC/ASIC Verification Results Trends
Resource (Verification Horizons Blog) - Jan 09, 2023 by Harry Foster
A metric often track to measure efficiency is ASIC project completion compared to the original schedule, as shown in Figure 12-1. Here we found that 66 percent of IC/ASIC projects were behind schedule, while 27% of projects were behind schedule by 27 percent.
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Part 11: ASIC/IC Low Power Trends
Resource (Verification Horizons Blog) - Jan 02, 2023 by Harry Foster
As shown in figure 11-1, we found that 72% of design projects actively manage power. In fact, we found that the larger the design, the greater the concern for power management. Obviously, a wide variety of techniques, ranging from simple clock-gating to complex hypervisor/OS-controlled power management schemes are employed whose requirements require verification.
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Siemens Xcelerator Academy: One Glance - All Trainings
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Guide Your Learning Journey With @oneGlance Maps. Use the maps as visual guides of the recommended flow of learning. Each course entry shows available method of delivery and is linked to course datasheets and sign-up requests.
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Learning Center: QuestaSim Training (Instructor Led)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Questa Core: HDL Simulation teaches users who are new to using Questa SIM for HDL simulation how to effectively use Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Also, you will receive an introduction on how to invoke the Visualizer debug environment to debug the simulation results from Questa.
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Learning Center: QuestaSim Training (On-Demand)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Gain mastery of Advanced Questa Simulator’s capabilities to manage your advanced verification environments and debug verification bugs.
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Learning Center: Visualizer Training (On-Demand)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
The Visualizer course will help you to effectively use Visualizer™ Debug Environment to verify your design and explore your UVM based testbench.
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Learning Center: Visualizer Training (Instructor Led)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
The Visualizer course will help you to effectively use Visualizer™ Debug Environment to verify your design and explore your UVM based testbench.
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Functional Verification: Self-Paced Library
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
This library contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use ModelSim/Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations. UVM Framework Verification IP ModelSim / Questa / Visualizer CDC / Lint / HDL Designer Much more 12 month subscription, On-Demand Training
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SystemVerilog for Verification: Self-Paced Course
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Learn about SystemVerilog fundamental and advanced verification constructs. SystemVerilog for Verification / Exam 12 month subscription, On-Demand Training
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SystemVerilog UVM: Self-Paced Course
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Learn how to create a reusable testbench from ground up using SystemVerilog UVM (Universal Verification Methodology) and how to add a UVM Register Model. SystemVerilog UVM / Exam UVM Intermediate / Exam 12 month subscription, On-Demand Training