Search Results

Advanced Search

2143 Results

Analog Aspects in AMS

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the main aspects that affect the Quality of an Analog design and introduces the possible means to address those areas.
Overview to Improve AMS Quality

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the challenges in improving Mixed-Signal Verification Quality.
AMS Design Configuration Schemes

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces a tool can be adapted in various topologies supporting the available methodologies with little or no impact on the design flow.
Mixing Languages

Session - Jan 25, 2013 by Ahmed Eisawy

This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the process.
Design Topologies

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the 2 main design topologies: Analog-Centric Mixed-Signal Designs and Digital-Centric Mixed-Signal Designs
Design Methodologies

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the 2 main flows used in Mixed-Signal design environments: Bottom-Up Design Flow and Top-Down Design Flow.
Analog/Mixed-Signal Domain

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the definition for Mixed-Signal domain and addresses the three main areas for AMS design: functionality, robustness and reliability.
Overview to AMS Configuration

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the opposing powers in Design Methodologies and the concept of Mixed-Signal design environments. Challenges and techniques will also be covered.
Improve AMS Verification Performance

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces a tool that will help verify complex Mixed-Signal designs to reach the goal of successful first tape-out.
AMS Modeling Guidance

Session - Jan 25, 2013 by Ahmed Eisawy

This session attempts to offer some general guidelines in developing Models for the various Analog and Mixed-Signal domain.
Modeling Abstraction

Session - Jan 25, 2013 by Ahmed Eisawy

This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the results.
AMS Engines

Session - Jan 25, 2013 by Ahmed Eisawy

This session covers the 2 main simulator technologies used in Mixed-Signal verification: AMS Simulation and Analog/Digital Co-Simulation.
Overview to Improve AMS Performance

Session - Jan 25, 2013 by Ahmed Eisawy

This session introduces the challenges in Mixed-Signal verification performance.
VHDL-2008 Overview

Session - Jan 18, 2013 by Jim Lewis

This session is a brief overview of all the VHDL-2008 improvements.
Testbench Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session examines testbench enhancements and the value they deliver.
RTL Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session examines the RTL enhancements in VHDL-2008 and the value they deliver.
Operator Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session will discuss the value of the many new enhancements to the VHDL-2008 operators.
Package Type Enhancements

Session - Jan 18, 2013 by Jim Lewis

The session explores the new packages and modifications to the packages as well as the value these updates deliver.
Fixed Point Package

Session - Jan 18, 2013 by Jim Lewis

This session will explain the details of the new fixed point package.
Floating Point Package

Session - Jan 18, 2013 by Jim Lewis

This session will explain the details of the new floating point package.
VHDL-2008 Why It Matters

Track - Jan 17, 2013 by Jim Lewis

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.
Effectively Modeling and Analyzing Coverage

Webinar - Nov 15, 2012 by Tom Fitzpatrick

In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.
ST-Ericsson Speeds Time to Functional Verification Closure with Questa

Article - Oct 01, 2012 by Rachida El IDRISSI - ST-Ericsson

Functional verification is one of the most critical steps in the IC development cycle. As complexity increases, along with the associated cost of fixing late-stage functional defects, manufacturers including ST-Ericsson are putting additional effort into the up-front verification process.
The Top Five Formal Verification Applications

Article - Oct 01, 2012 by Roger Sabbagh - Siemens EDA

It's no secret. Silicon development teams are increasingly adopting formal verification to complement their verification flow in key areas. Formal verification statically analyzes a design's behavior with respect to a given set of properties.
Three Steps to Unified SoC Design and Verification

Article - Oct 01, 2012 by Mark Peryer

Developing a SoC is a risky business in terms of getting it right considering the technical complexity involved, managing the mixture of hardware and software design disciplines, and finding an optimal trade-off between design performance and power. One way to reduce these risks is to use a design and verification flow that is scalable enough to handle the complexity and is flexible enough to explore architectural alternatives early in the design cycle before implementation starts.