Traffic Profiling and Performance Instrumentation For On-Chip Interconnects
This paper describes a proposal for the specification of bus master traffic profiles and system level traffic scenarios, together with the definition of performance metrics that need to be instrumented to ensure that an interconnect is meeting its performance targets.
Full-access members only
Register your account to view Traffic Profiling and Performance Instrumentation For On-Chip Interconnects
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.