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The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient

Article - Jun 01, 2013 by Shobana Sudhakar

The intent of this article is to educate customers and guide them to understand what makes a design multicore friendly. This can help customers write designs and testbenches to be more suited for parallel simulations. Cases of success and failures of QuestaSim MC2 deployments and the lessons learned from them form the basis of our analysis and substantiate our suggestions in this article.
An Enhanced UPF Example

Session - May 31, 2013 by Chuck Seeley

This session presents an extended example illustrating the usage of the UPF 2.0 features of IEEE Std 1801 UPF for specification of the power management architecture for a simple design.
Using Supply Sets

Session - Apr 29, 2013 by Chuck Seeley

This session presents the UPF 2.0 concept of a “supply set” and the related commands and options used for defining and using supply sets.
UPF 2.0 Enhancements

Session - Apr 08, 2013 by Chuck Seeley

This session presents UPF 2.0 commands and options that improve usability and provide greater flexibility.
A Simple UPF Example

Session - Apr 08, 2013 by Chuck Seeley

This session presents an extended example illustrating the usage of the UPF 1.0 subset.
Getting Started with UPF

Session - Apr 08, 2013 by Erich Marschner

This session presents the core commands and options in UPF 1.0 subset.
Introduction to Power Aware Verification

Session - Apr 08, 2013 by Erich Marschner

This session introduces the IEEE Std 1801 Unified Power Format (UPF).
Overview of UPF

Session - Apr 08, 2013 by Erich Marschner

This session gives a quick, high-level overview of the evolution of the UPF standard.
Power Aware Verification

Track - Apr 05, 2013 by Erich Marschner

This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.
Functional Verification Study - 2012

Session - Apr 01, 2013 by Harry Foster

In this session, Harry Foster highlights the key findings from the 2012 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
UVM 1.1d Class Reference

Resource (Reference Documentation) - Mar 07, 2013 by

v1.1d The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
Boost Verification Results by Bridging the Hardware/Software Testbench Gap

Paper - Feb 27, 2013 by Matthew Ballance

Today's complex designs increasingly include at least one, and often more, embedded processors. Given software's increasing role in the overall design functionality, it has become increasingly important to leverage the embedded processors in verifying hardware/software interactions during system-level verification. This paper presents a UVM-based package for software-driven verification and presents applications of this package that enable more-comprehensive system-level verification.
Register Verification: Do We Have Reliable Specification?

Paper - Feb 27, 2013 by Wesley Park - Siemens EDA

Traditional register verification uses simulation to check IP compliance with a manually written specification. In this paper, we introduce a register model that overcomes limitations in the expressiveness of the predefined UVM and IPXACT access polices. We will also present results from the successful application of our method to the register verification of three industrial designs.
Register Verification: Do We Have Reliable Specification?

Resource (Paper (.PDF)) - Feb 27, 2013 by Wesley Park - Siemens EDA

In this paper, we introduce a register model that overcomes limitations in the expressiveness of the predefined UVM and IPXACT access polices. We will also present results from the successful application of our method to the register verification of three industrial designs.
Boost Verification Results by Bridging the Hardware/Software Testbench Gap

Resource (Paper (.PDF)) - Feb 27, 2013 by Matthew Ballance

This paper presents a UVM-based package for software-driven verification and presents applications of this package that enable more-comprehensive system-level verification.
Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

Resource (Paper (.PDF)) - Feb 27, 2013 by Mike Horn

With parameterized agents, driver level data rate controls and timing controls in addition to utilizing the broad capabilities of OVM and UVM, the GOES-R C&DH team produced FPGAs that performed admirably in the lab.
Methodology Enhancements used on a Next Generation Weather Satellite C&DH Program

Paper - Feb 27, 2013 by Mike Horn

In 2010–2011, Lockheed Martin Space Systems designed and verified eight FPGAs for the Command and Data Handling (C&DH) subsystem of the NOAA/NASA Geostationary Operational Environmental Satellite R-Series (GOES-R), scheduled to launch in 2015. Hardware validation and integration of these FPGAs went smoothly. Perhaps the best measure of the success: the FPGAs performed with almost no functional failures during integration and test.
Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog

Resource (Recording) - Feb 27, 2013 by Adam Erickson

UVM Connect bridges the SystemC and SystemVerilog language boundary to provide seamless TLM1 and TLM2 connectivity between components residing in those two languages.
Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog

Paper - Feb 27, 2013 by Adam Erickson

This paper describes the purpose, requirements, development challenges, and applications of an open-source library for establishing standard TLM-based communication between SystemC (SC) and SystemVerilog (SV) models, including C/C++ models wrapped in SC or SV. It also describes a SystemC-side interface for controlling simulations based on the UVM in SystemVerilog. The UVM Connect library is available for download and has been proven to work on three major EDA vendors’ simulators. 1
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

Resource (Paper (.PDF)) - Feb 26, 2013 by Mark Peryer

This paper describes a proposal for the specification of bus master traffic profiles and system level traffic scenarios, together with the definition of performance metrics that need to be instrumented to ensure that an interconnect is meeting its performance targets.
Traffic Profiling and Performance Instrumentation For On-Chip Interconnects

Paper - Feb 26, 2013 by Mark Peryer

On-chip bus interconnect fabrics have become critical sub-systems in SoC platforms. Not only do they need to be functionally correct, but they also need to deliver the performance demanded by user applications. This paper describes a proposal for the specification of bus master traffic profiles and system level traffic scenarios, together with the definition of performance metrics that need to be instrumented to ensure that an interconnect is meeting its performance targets.
Seven Separate Sequence Styles Speed Stimulus Scenarios

Resource (Paper (.PDF)) - Feb 26, 2013 by Mark Peryer

This paper describes seven common sequence design patterns which should prove useful to all UVM sequence writers. These patterns can be used stand-alone or combined to solve practical stimulus generation problems using UVM sequences.
Sequence, Sequence on the Wall: Who's the Fairest of Them All?

Paper - Feb 26, 2013 by Rich Edelman

The reader of this paper is interested to use UVM sequences to achieve his test writing goals. Examples of UVM sequences will be used to demonstrate basic and advanced techniques for creating interesting, reusable sequences and tests.
Seven Separate Sequence Styles Speed Stimulus Scenarios

Paper - Feb 26, 2013 by Mark Peryer

Writing effective stimulus in UVM can prove to be challenging for various reasons, but not knowing about the relevant coding design patterns should not be one of them. There are various alternative techniques for writing sequences and choosing the right approach requires mastery of several styles. This paper describes seven common sequence design patterns which should prove useful to all UVM sequence writers.
Boosting Simulation Performance of UVM Registers in High Performance Systems

Resource (Paper (.PDF)) - Feb 26, 2013 by Ahmed Yehia - Siemens EDA

In the paper, we give a quick overview of the UVM register library on how it could be used to model and verify hardware registers and memory blocks, showing the simulation performance bottlenecks observed when performing on high-speed buses.