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Use Formal to Check Logic Faults

Webinar - Mar 17, 2017 by Mark Eslinger

In this session, you will learn how to use Formal to check if your RTL is sensitive to any logic faults, and how can you verify that the internal safety mechanism handles them to avoid a catastrophic failure.
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee

Paper - Mar 13, 2017 by Thomas Ellis

As verification engineers, we are always looking for ways to automate otherwise manual tasks. In case you have not heard, we are constantly trying to do more with less. Continuous Integration is a practice which has been widely and successfully used in the software realm for many years. Deploying a continuous integration server such as Jenkins not only provides a way to automate the running of jobs, and collection of results, allowing teams to reap the benefits of a continuous integration.
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee

Resource (Poster Paper) - Mar 13, 2017 by Thomas Ellis

Among many other benefits, Jenkins also provides a web dashboard to view and analyze results in a common place, regardless of how spread out your team may be. Its open source, has a strong community behind it, and you can start seeing the benefits by getting it up and running a regression in your environment before you even finish your morning cup of coffee.
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee

Resource (Paper (.PDF)) - Mar 13, 2017 by Thomas Ellis

Deploying a continuous integration server such as Jenkins not only provides a way to automate the running of jobs, and collection of results, but it also allows for teams to reap the benefits of a continuous integration practices, which ultimately leads to a cleaner repository, with less integration headaches.
Will Safety Critical Design Practices Improve First Silicon Success?

Article - Mar 01, 2017 by Harry Foster

For this issue of Verification Horizons, I have decided to do a deeper dive into our 2016 industry study and see what other non-intuitive observations could be uncovered. Specifically, I wanted to answer the following questions: (1) Does verification maturity impact silicon success (in terms of functional quality)? (2) Does the adoption of safety critical design practices improve silicon success?
A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products

Article - Mar 01, 2017 by Jamil R. Mazzawi, Amir N. Rahat - Optima Design Automation Ltd.

In this article, we present a simple, easy step-by-step methodology to comprehend and achieve functional safety from random faults based on Questa® simulation and the fault-injection accelerator from Optima.
Automating Tests with Portable Stimulus from IP to SoC Level

Article - Mar 01, 2017 by Matthew Ballance

Portable stimulus seeks to raise the level of abstraction and enable users to automate testing of the complex scenarios that emerge in subsystem- and SoC-level verification. However, the PSS under development by the Accellera PSWG builds on the base of constraint-based, transaction-level verification, which is already well-understood and widely deployed today.
UVM Tips and Tricks

Article - Mar 01, 2017 by Sandeep Nasa, Shankar Arora - Logic Fruit Technologies Pvt. Ltd.

UVM is the most widely used Verification methodology for functional verification of digital hardware (described using Verilog, SystemVerilog or VHDL at appropriate abstraction level). It is based on OVM and is developed by Accellera. It consists of base libraries written in SystemVerilog which enables the end user to create testbench components faster using these base libraries.
Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation

Article - Mar 01, 2017 by Progyna Khondkar

The Questa Power Aware (PA) dynamic simulator (PA-SIM) provides a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from target design implementation objectives.
Complementing Functional Verification Through the Use of Available Timing Information

Article - Mar 01, 2017 by Rick Eram - Excellicon

Since the advent of formal techniques, the application of formal analysis has helped designers achieve more in-depth analysis and coverage of functional verification activities in general. However what has spurred the growth and popularity of such techniques has been specific and targeted applications of formal analysis.
How Formal Reduces Fault Analysis for ISO 26262

Paper - Feb 15, 2017 by Doug Smith

In this white paper, we will discuss how to use formal verification for static and transient fault analysis to generate the ISO 26262 safety metrics. First, we will look at some of the low-hanging fruit that formal analysis provides, and then we will discuss how to tackle the much harder task of fault injection.
How Formal Reduces Fault Analysis for ISO 26262

Resource (Paper (.PDF)) - Feb 15, 2017 by Doug Smith

This paper discusses how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.
Questa VRM and Jenkins

Track - Jan 10, 2017 by Darron May

This track will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.
Jenkins Installation and Setup

Session - Jan 10, 2017 by Darron May

In this session you will be introduced to the Jenkins continuous integration system, along with step by step installation and setup instructions.
Jenkins Project Configuration

Session - Jan 10, 2017 by Darron May

In this session we will walk through the project configuration and how to setup a job with the Questa VRM plug-in.
Jenkins VRM Integration

Demo - Jan 10, 2017 by Darron May

In this session, we will demo the Questa VRM Jenkins integration and you will see first hand how to execute tests and generate reports.
The Fundamental Power States for UPF Modeling and Power Aware Verification

Article - Jan 04, 2017 by Verification Methodology Team
Introspection Into SystemVerilog Without Turning It Inside Out

Article - Jan 03, 2017 by Dave Rich
Extending a Traditional VIP to Solve PHY Verification Challenges

Article - Jan 03, 2017 by Verification Methodology Team
Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI

Article - Jan 03, 2017 by Dave Rich
UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process

Article - Jan 03, 2017 by Verification Methodology Team
Equivalence Validation of Analog Behavioral Models

Article - Jan 03, 2017 by Verification Methodology Team
Interpreting UPF For A Mixed-Signal Design Under Test

Article - Jan 03, 2017 by Verification Methodology Team
Using Test-IP Based Verification Techniques in a UVM Environment

Article - Jan 03, 2017 by Verification Methodology Team
Is Your Power Aware Design Really X-Aware?

Article - Jan 03, 2017 by Verification Methodology Team