New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific


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    Authors: Kenneth Bakalar - Mentor GraphicsEric Jeandeau - Mentor Graphics Abstract: IEEE Std 1801-2009 (1) defines the Unified Power Format (UPF) for specifying power distribution and control information required by digital RTL and gate models to represent the structure and behavior of designs with active power management. We propose an interpretation of UPF for designs that include analog and mixed signal elements coded in Verilog-AMS, VHDL-AMS, or SPICE. No changes to the UPF syntax or file are required. We offer as proof of concept a complete implementation and a demonstration of its use in a sample case. The implementation consists of a modified elaborator and an extensible set of power-aware interface elements. Introduction: The digital register-transfer level (RTL) abstraction incorporates the unstated assumption that sufficient power is always available for the system to operate correctly after simulation time zero. The increasing importance of power consumption in electronic systems invalidates this assumption and creates a need for a model of active power management that supplements the RTL abstraction (2). UPF provides the necessary notation for modeling active power control of digital RTL designs. In contrast, low-level electrical designs—traditionally coded in SPICE and, more recently, SPICE combined with the mixed-signal languages VHDL-AMS and Verilog-AMS—model the power supply and power control explicitly. Electrical models are fundamentally dependent on appropriate power for correct operation, and in this they are unlike functional models at the RTL. Two new problems are salient in analog and mixed-signal (AMS) practice that do not arise in homogeneous digital or electrical design hierarchies. The first problem arises at the boundary between abstractions, when a composite hierarchy combines and connects elements from the electrical and digital domains. The second occurs because the power sources and power control defined by UPF that supplement an RTL hierarchy must be interpreted to include the power sources and controls of the AMS hierarchical descendants as well. To resolve these issues we propose, a method for providing UPF-controlled, SPICE-level power to those AMS instances that require it, and a method for defining signal connect elements (connect modules) that are sensitive to the supply set of the drivers and/or receivers of a port. The use model for UPF in an AMS design described in the following paragraphs provides a guiding context for the design and implementation we describe in the net section. We assume the engineer begins with a power-aware design described by a homogeneous digital hierarchy and an accompanying UPF file. An instance of an AMS model (coded in SPICE, Verilog-AMS, or VHDL-AMS) with electrical ports will be substituted for an existing digital instance in the digital design. The AMS model has electrical ports that correspond one-for-one to the ports of the digital instance that will be replaced. The translation of information to and from the electrical ports should be transparent to the instantiating digital circuit. The translation should be sensitive to the supply set of the UPF domains containing the drivers and/or receivers of the digital signals. The AMS model also has additional electrical ports that supply power to the analog sub-circuit within the model. The analog power supplies connected to the ports must be synchronized with the power state of the UPF power domain of the instance. Alternatively, the model may contain the root supply driver for a power function of the enclosing power domain—that is, the model acts as a producer rather than a consumer of power. In that case, the port must be interpreted as the root of a UPF power net. View & Download: Read the entire Interpreting UPF For A Mixed-Signal Design Under Test technical paper. Download the presentation slides. Source: DVCon 2014