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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific

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    Authors: Durgesh Prasad - Mentor GraphicsJitesh Bansal - Mentor Graphics Abstract: X-optimism is a precarious problem in RTL simulation. It can hide X bugs to cause serious issues in real silicon. Such hidden bugs are aggravated in power aware simulation due to injection of additional 'X' from power down regions. Traditional verification techniques such as tool generated assertions [4] and custom bind checkers [5] cannot catch such issues. Nowadays a new technique X-propagation is used to catch x-optimism related issues in RTL simulation. But this technique lacks the knowledge of power intent of design, causes unnecessary noise, and therefore not very useful in power aware simulation. In this paper, the authors would describe an effective technique to catch x related issues such as reset failures, wake up failures and x-optimism issues in power aware simulation. In this paper we present a method to use power aware knowledge on existing x-propagation technique for comprehensive x verification which is fully automated and provides ease of debug. Our solution will selectively apply X propagation technique according to system power state in a controlled way. This dynamic selection and controlability would ensure minimal noise, relevant x-propagation and better debug capability. The propagated x values can be observed in simulation waveforms and debug tools. This will catch x-optimism issues in a power aware simulation which are known to cause design failure at synthesis level. Also, our solution will automatically insert SystemVerilog assertions to catch x-errors at the source. These assertions would be active according to current simstate of the system and they can also be used as an alternate for custom bind checker or low power assertion checks. This solution has advantage that it is fully automatic, comprehensive and free from user input. The downside is that it could generate some noise because the RTL morphing could be overly pessimistic. In the paper we will further discuss the tradeoffs and methodology in detail. Introduction: Power Aware verification has become increasingly critical for the semiconductor industry. Due to shrinking process geometry designers are focusing more on reducing static and dynamic power and it puts immense burdens on verification teams to ensure complete power aware verification. The common trend is to start power aware verification once functional RTL verification is complete. The power aware behavior is imparted on the functional RTL design using UPF and liberty cells (optional). The various EDA vendors provide simulation tools to verify powers aware techniques like power shut-off, back-biasing and voltage scaling using UPF. In simulation context these techniques are verified using corruption which means injecting x values on the signals of concern and propagating them further down the logic. These x-values require a competent handling, efficient tracking and painless debugging. In recent past there have been significant investments in this area and as a result good debug tools, faster power aware simulation and low-power assertion checks have been developed. Although these are good at catching x related issues visible at RTL level, they fail to catch certain silicon related issues arising due to x-optimism of RTL. X-optimism [1] is when there is some uncertainty on an input to an expression or gate (the silicon value might be 0 or 1), but simulation comes up with a known result instead of X .For example SystemVerilog has an optimistic behavior when the control condition of an if...else statement is unknown. View & Download: Read the entire Is Your Power Aware Design Really X-Aware? technical paper. Source: DVCon 2014