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Environment Code Generation

Session - Feb 26, 2018 by Jonathan Craft

In this session, you will learn the format and content of the YAML configuration file that describe the UVMF Environment.
Environment Code Generation

Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
Scoreboards and Predictors

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn the roles and responsibilities of scoreboards and predictors within the UVMF, the scoreboards provided by UVMF and how they are configured.
Scoreboards and Predictors

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Environments: Architecture and Operation

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Environments: Architecture and Operation

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn the roles and responsibilities of an environment within a simulation.
Interface Code Generation

Session - Feb 26, 2018 by Jonathan Craft

In this session, you will learn the steps needed to produce code for an UVMF Interface using the generator.
Interface Code Generation

Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
Agents: Architecture and Operation

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
Agents: Architecture and Operation

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn about components within a protocol agent and its associated bus functional models and the roles and responsibilities of these components including the abstraction level they operate at.
Code Generation Introduction

Resource (Slides (.PDF)) - Feb 26, 2018 by Jonathan Craft
Code Generation Introduction

Session - Feb 26, 2018 by Jonathan Craft

In this session, you will learn why code generation can be a powerful tool and how to take advantage of it for the purposes of quickly producing a UVMF-based testbench.
UVMF - Overview

Session - Feb 26, 2018 by Bob Oden

In this session, you will learn what the UVM Framework is, the functionality it provides, its testbench architecture, and available documentation and support.
UVMF - Overview

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
UVMF - Series Introduction

Resource (Slides (.PDF)) - Feb 26, 2018 by Bob Oden
UVMF - Series Introduction

Session - Feb 26, 2018 by Bob Oden

In this session, you are introduced to the UVM Framework and the list of sessions that comprise this video track.
UVM and C Tests: Perfect Together

Resource (Paper (.PDF)) - Feb 26, 2018 by Rich Edelman

This paper will demonstrate techniques and methods for using DPI-C along with a standard UVM Testbench.
UVM Framework (UVMF)

Track - Feb 26, 2018 by Bob Oden

In this track you will learn more about UVM Framework (UVMF) and how it that provides a reusable UVM methodology and code generator for rapid testbench generation.
UVM and C Tests: Perfect Together

Paper - Feb 26, 2018 by Rich Edelman

Using DPI-C is easy and powerful. Using a SystemVerilog interface, many of the integration and connection issues can be eliminated. Using the techniques outlined above large, threaded C tests can be created easily. This paper will demonstrate techniques and methods for using DPI-C along with a standard UVM Testbench.
Low Power Coverage: The Missing Piece in Dynamic Simulation

Paper - Feb 24, 2018 by Progyna Khondkar

In this paper, you will learn that low power (LP) design verification is an emerging technology, and almost every chip design today incorporates UPF (IEEE-1801 standard) based power dissipation and reduction techniques to manage and control the power on chip. Coverage data from LP verification in general originates from UPF and relevant HDL objects, i.e. power domains, power supplies, power states, different power strategies, control signals and ports of the power strategies.
Low Power Coverage: The Missing Piece in Dynamic Simulation

Resource (Paper (.PDF)) - Feb 24, 2018 by Progyna Khondkar

In this paper, you will learn how to achieve comprehensive LP design verification closure with all possible sources of power states, their transition coverage and cross-coverage of power domains of interdependent states. As well the paper also proposes the mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with API accessibility.
Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

Webinar - Dec 12, 2017 by Neil Bulman

This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.
How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety

Article - Dec 05, 2017 by Dan Alexandrescu, Adrian Evans, Maximilien Glorieux - IROC Technologies

In this article, we present a working example, implemented using the Questa Verification Platform where a 32-bit RISC V CPU has been subjected to an extensive static and dynamic failure analysis process, as a part of a standard-mandated functional safety assessment.
Step-by-Step Tutorial for Connecting Questa VIP into the Processor Verification Flow

Article - Dec 05, 2017 by Marcela Zachariasova, Lubos Moravec - Codasip, Ltd.

This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification environments by QVIP Configurator and Questa® VIP (QVIP) components. The section with step-by-step instructions will demonstrate how to add QVIP components into processor verification environments.
PA GLS: The Power Aware Gate-level Simulation

Article - Dec 05, 2017 by Progyna Khondkar

In post-synthesis, gate-level netlist (GL-netlist), power aware (PA) simulation, the fundamental focus is to identify PA specific cells already present in the netlist. The associated UPF with the netlist design, determines the supply network and power connectivity to these special PA cells, and aid to keep their outputs from being corrupted. Hence, the GL-netlist-based power aware simulation (PA-SIM) input requirements are mostly the same as for RTL simulation.