Search Results

Advanced Search

2212 Results

Formal Techniques for Optimizing ISO 26262 Fault Analysis

Resource (Paper (.PDF)) - Feb 28, 2019 by Doug Smith

The automotive safety standard, ISO 26262 [1], states that safety analyses on hardware designs should include Failure Mode and Effects Analysis (FMEA). Hardware architectural metrics are required to assess the adequacy of the safety mechanisms and their ability to prevent faults from reaching safety critical areas. A process of fault analysis that includes fault injection is crucial for measuring and verifying the assumptions of the FMEA.
Using Strong Types in SystemVerilog Design and Verification Environments

Resource (Paper (.PDF)) - Feb 28, 2019 by Dave Rich
Ten Rules to Successfully Deploy Formal

Article - Feb 25, 2019 by Dr. Ashish Darbari

About four years ago I gave a couple of talks on the myths surrounding formal. Although, formal has seen more adoption since then, we have a long way to go before it is recognized as a mainstream technology used throughout design and verification. I still see some of these myths clouding the judgement of end users and their managers.
Formal Apps Take the Bias Out of Functional Verification

Article - Feb 25, 2019 by Bill Au

When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This is why verification engineers have a blind spot for their own verification platforms. This blind spot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.
Simplifying Assertion Validation Using UVM Callbacks

Article - Feb 25, 2019 by Arushi Jain - Siemens EDA

An assertion is a conditional statement that indicates the incorrect behavior of a design by flagging an error and thereby catching bugs. Assertions are used for validating a hardware design at different stages of its life-cycle, such as formal verification, dynamic validation, runtime monitoring, and emulation.
Effective Elements Lists and the Transitive Nature of UPF Commands

Article - Feb 25, 2019 by Progyna Khondkar

In this article, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inherent features help to foster and establish exact relationships between UPF and DUT objects in order to develop UPF for power management and implementation as well as conduct power aware verification.
Selecting a Portable Stimulus Application Focal Point

Article - Feb 25, 2019 by Matthew Ballance

As designs, especially System on Chip designs, have become more complex, the need for generated good, automated stimulus across the verification spectrum has increased. Today, the need for verification reuse and automated stimulus is clearly seen from block to subsystem to SoC-level verification.
Choosing a Format for the Portable Stimulus Specification

Resource (Paper (.PDF)) - Feb 22, 2019 by Matthew Ballance

This white paper discusses portable stimulus, the industry’s solution for verification portability up and down the design hierarchy and across platforms.
Low Power Verification Forum

Webinar - Feb 05, 2019 by Gordon Allan

In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.
Industry Advancements Required to Close the Power Management Verification Gap

Webinar - Jan 28, 2019 by Sriram Hariharan

In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.
Deploying a Metrics Driven Low Power Methodology for Your RTL IP

Webinar - Jan 28, 2019 by Qazi Ahmed

In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.
Low Power Verification & Analysis with Emulation

Webinar - Jan 28, 2019 by Shantanu Samant

In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.
Productive Low Power Debug Across All Engines and Flows

Webinar - Jan 28, 2019 by Gordon Allan

In this session, we will answer the top nine questions asked for debugging low power in your design.
Accelerating Verification through Verification IP, Configurator and UVM Framework

Resource (Slides (.PDF)) - Jan 24, 2019 by Sharath Kannareddy
Making Verification Fun Again

Resource (Slides (.PDF)) - Jan 24, 2019 by Jonathan Craft
Verification Acceleration for FPGA Designs with Matlab

Resource (Slides (.PDF)) - Jan 24, 2019 by Jerry Grula - Siemens EDA
Welcome & Overview

Resource (Slides (.PDF)) - Jan 24, 2019 by Harry Foster
ASIC & FPGA SoC Functional Verification Trends

Resource (Slides (.PDF)) - Jan 24, 2019 by Harry Foster
How to Unearth Deep Bugs Faster and Cheaper Using Formal Bug Hunting Techniques

Webinar - Dec 23, 2018 by Mark Eslinger

In this session, you will learn how to leverage formal analysis to find and fix as many functional bugs as possible, ultimately improving the quality of your end-product, and lowering the risk of re-spins.
Effective Elements List and Transitive Natures of UPF Commands

Resource (Paper (.PDF)) - Dec 21, 2018 by Progyna Khondkar

It is evident now that UPF commands-options are inherently transitive in nature through the implicit or explicit – transitive option. With the progression of UPF versions and revisions from UPF 2.0 to 2.1 and onward, the transitive nature becomes more realistic and consistent with all UPF semantics, specifically for UPF strategies, as well as for UPF and DUT objects.
Effective Elements List and Transitive Natures of UPF Commands

Paper - Dec 21, 2018 by Progyna Khondkar

The UPF commands are, in general, transitive in nature. For example, for any given instance included in a power domain, all child instances of that given instance are transitively included in the power domain, unless any child instance is explicitly excluded from this particular power domain or is explicitly included in the definition of another power domain.
Full-Featured SOC Debug Cross-Triggering

Article - Dec 10, 2018 by Verification Methodology Team
C Stimulus Package (.tgz)

Resource (Tarball) - Dec 04, 2018 by Verification Methodology Team
FPGA Verification Challenges and Opportunities

Article - Nov 28, 2018 by Harry Foster

There have been multiple studies on IC/ASIC functional verification trends published over the years. 1,2,3,4 However, there are no published studies specifically focused on Field-Programmable Gate Array (FPGA) verification trends.
Building a Better Virtual Sequence with Portable Stimulus

Article - Nov 28, 2018 by Matthew Ballance

When using the Universal Verification Methodology (UVM), sequences are the primary mechanism by which stimulus is generated in the testbench. Sequences come in two flavors: simple sequences for driving a single interface, and virtual sequences that control more complex behavior. Simple sequences tend to work with a single sequence item, while virtual sequences often spawn off multiple sub-sequences to accomplish their intended task.