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82 Results

• Testbench Automation - Testbench

  Webinar - Mar 17, 2017 by Matthew Ballance

  In this session, you will learn how Portable Stimulus shortens the time to create efficient, systematic scenario-level stimulus.

• Testbench Automation - Interfaces

  Webinar - Mar 17, 2017 by Bob Oden

  In this session, you will learn how to use a VIP Configurator to shorten the bring up time for industry standard protocols.

• Questa Verification IP Configurator

  Webinar - Nov 14, 2016 by Dave Aerne

  In this session you learn how Questa Verification IP configurator can be used not only to instantiate and configure Questa VIP components, but also to generate a complete testbench that can be used stand-alone, or integrated into a larger UVM or UVM Framework (UVMF) based environment.

• Productive Verification with VIP, a UVM Framework and Configuration GUI

  Webinar - Nov 11, 2016 by Jason Polychronopoulos

  In this session, you will learn how to leverage Verification IP and the UVM Framework to create a running testbench without writing any SystemVerilog code.

• UVM Framework – Create a UVM Environment in Less than an Hour

  Webinar - Nov 25, 2015 by Bob Oden

  In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.

• UVM Framework – Create a UVM Environment in Less than an Hour

  Resource (Slides) - Nov 25, 2015 by Bob Oden

  In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.

• Establishing a Company Wide Verification Reuse Library

  Webinar - Oct 15, 2014 by Bob Oden

  In this session, you will learn how to outline key characteristics of a reuse verification library and will outline a proven reuse methodology.