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77 Results

• Reusable UPF - Transitioning from RTL to Gate Level Verification

  Resource (Technical Paper) - Jun 11, 2019 by

• Random Directed Low-Power Coverage Methodology - A Smart Approach to Power Aware Verification Closure

  Resource (Technical Paper) - May 22, 2019 by Madhur Bhargava

  With the advancement in the technology, low-power design and its verification is becoming more complex. Today’s chips have multiple power domains each having multiple operating power modes and dynamically changing voltage levels.

• Effective Elements List and Transitive Natures of UPF Commands

  Resource (Technical Paper) - Feb 28, 2019 by

• Low Power Apps: Shaping the Future of Low Power Verification

  Resource (Technical Paper) - Feb 28, 2019 by

• Effective Elements Lists and the Transitive Nature of UPF Commands

  Article - Feb 25, 2019 by Progyna Khondkar

  In this article, we provide a simplistic approach to find inherent links between UPF commands-options through their transitive nature. We also explain how these inherent features help to foster and establish exact relationships between UPF and DUT objects in order to develop UPF for power management and implementation as well as conduct power aware verification.

• Low Power Verification Forum

  Webinar - Feb 05, 2019 by Gordon Allan

  In this session, you will be introduced to new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture.

• Industry Advancements Required to Close the Power Management Verification Gap

  Webinar - Jan 28, 2019 by Sriram Hariharan

  In this session, you will learn how Qualcomm overcomes their power verification challenges and how they utilize power aware verification techniques.

• Deploying A Metrics Driven Low Power Methodology for Your RTL IP

  Webinar - Jan 28, 2019 by Qazi Ahmed

  In this session, you will learn how PowerPro is a single solution for RTL audit, power optimization, estimation and exploration.

• Low Power Verification & Analysis with Emulation

  Webinar - Jan 28, 2019 by Shantanu Samant

  In this session, you will learn how Emulation techniques can be used for low power verification including power analysis and power estimation.

• Productive Low Power Debug Across All Engines and Flows

  Webinar - Jan 28, 2019 by Gordon Allan

  In this session, we will answer the top nine questions asked for debugging low power in your design.

• A New Approach to Low Power Verification: Power Aware Apps

  Article - Nov 28, 2018 by Madhur Bhargava, Awashesh Kumar - Siemens EDA

  The effective verification of low-power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs.

• UPF Information Model: The Future of Low-Power Verification Today

  Paper - Aug 28, 2018 by Progyna Khondkar

  The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.

• UPF Information Model - The Future of Low-Power Verification Today

  Resource (Technical Paper) - Aug 28, 2018 by Progyna Khondkar

  The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.

• Power Aware Simplifies Parametric PA-SIM Regression

  Resource (Slides) - Aug 02, 2018 by

• Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs

  Article - Jun 29, 2018 by Progyna Khondkar

  Part I of this article provided a consolidated approach to understand verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structures of the design.

• Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs

  Webinar - Mar 07, 2018 by Ellie Burns

  In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.

• SATA Specification 3.3 Gaps Filled by SATA QVIP

  Article - Mar 01, 2018 by Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens EDA

  Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.

• From Power Intent to Microarchitectural Checks of Low-Power Designs - Part 1

  Article - Mar 01, 2018 by Progyna Khondkar

  PA-Static verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF).

• PA GLS: The Power Aware Gate-level Simulation

  Article - Dec 06, 2017 by Progyna Khondkar

• Low-Power Design using High-Level Synthesis for Automotive Image Sensor

  Resource (Slides) - Aug 07, 2017 by

• Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

  Paper - Mar 20, 2017 by Progyna Khondkar

  Since UPF was first announced in 2007 by Accellera, many of the early features- like explicit supply port, supply net and the power state table (PST)- governed UPF based low power design verification methodologies mainly from post synthesis levels and onward. However, the recent update of IEEE 1801 3 specifies intrinsic flexibility to associate a power domain with a supply set and implicate infinite ordered list of power states, augmented with incrementally refinable arguments for the objects.

• Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF

  Resource (Technical Paper) - Mar 20, 2017 by Progyna Khondkar

  The recent edition of IEEE 1801 specifies the power state table (PST) construct should be phased out as legacy, and instead be replaced by the new semantics of the 'add_power_state' UPF command. This paper starts with investigating the limitations of legacy PST in a complex SoC design verification environment, and how to reap the benefits of the incrementally refinable power state features through the fundamental constructs of 'add_power_state'.

• Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation

  Article - Feb 28, 2017 by Progyna Khondkar

  The Questa Power Aware (PA) dynamic simulator (PA-SIM) provides a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from target design implementation objectives.

• The Fundamental Power States for UPF Modeling and Power Aware Verification

  Article - Jan 04, 2017 by Verification Methodology Team

• Is Your Power Aware Design Really X-Aware?

  Article - Jan 03, 2017 by Verification Methodology Team