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As I write this, my daughter is preparing for the opening night performance of Disney's "Peter Pan" with her youth theater group. Megan is featured as a mermaid and a Native American in the show, and in order to get pictures and video of her performance, I attended the dress rehearsal last night. This is our third season with the group, and I once again helped with set construction. I bring this up for two reasons. The first is to once again indulge your patience in my displaying a little fatherly pride in my daughter's theatrical accomplishments, and the second is to talk about reuse.

Yes, that's right: reuse.

As a small self-sustaining enterprise, with a limited budget and dependent on parent volunteers for things like set construction and costuming, the theater group relies on the idea of reuse as much as possible, for many of the same reasons we rely on reuse in verification. For example, the mermaid costumes are the same ones used last year in our production of "The Little Mermaid" and I recognized several other costumes as having been used in previous productions as well. Similarly, we reused several set pieces as well as hardware (hinges, casters, etc.) while creating the new set. In both cases, reusing existing pieces, with perhaps some customization, saved us both money and time. Aren't those always the two commodities we're trying to save in verification too? And, just like verification, we have schedule and quality goals that must be met as well.

In this issue, we have several articles that explore this idea of reuse through the use of Questa VIP components. The first, by my colleague Prashant Dixit of Mentor in India, discusses how you can "Integrate Ethernet QVIPs A-to-Z in a Few Hours," and shows how to instantiate a QVIP component quickly and easily into your UVM environment. In this informative article, you'll see how to instantiate and connect the QVIP component itself, and how to arrange your environment to configure the QVIP and take advantage of built-in protocol-specific analysis, coverage and debug features of the component.

In "Fast Track to Productivity Using Questa Verification IP," my colleagues Dave Aerne and Ankur Jain take you through a new set of productivity features that we've named "EZ-VIP" to simplify the tasks of instantiating, configuring and exercising Questa VIP for popular protocols like PCIe and AXI4. Through the use of predefined sequences, configuration objects and wrapper modules, EZ-VIP functions as a "Quick Starter Kit" to help you get up and running quickly to verify standard design IP.

We round out our VIP-related articles with "Cache-Coherent Interface Verification IP," in which my colleague Amit Kumar Jain extends the EZ-VIP discussion to focus on the use generic read/write APIs for ARM® AMBA® cache-coherent protocol verification. By also providing a coherency API as well as a cache controller in the VIP, the task of writing meaningful stimulus sequences becomes much simpler. Next, we change gears a bit with another article from one of my favorite authors, Josh Rensch, who shares his thoughts on "How Design Engineers Can Get Verification Engineers to Stop Complaining, and Other Advice." In this somewhat irreverent and refreshingly candid article, Josh delivers great advice to design engineers to help them avoid some of the more common pitfalls that cause tension between design and verification teams. This is a fun article with lots of useful information.

For those of you who were not able to attend the new DVCon India conference, we have a special treat for you. My colleagues Rich Edelman and Raghu Ardieshar won the Best Poster award at the conference, and we're happy to share this award-winning paper with you, in the article "Please! Can Someone Make UVM Easier to Use?" Rich and Raghu go through a series of "before" and "after" code examples to show you how to use just the right set of features in UVM to make your code clear, concise and easy to debug.

In our Partners' Corner of this issue, we start with "Controlling On-The-Fly Reset in a UVM-Based AXI Testbench Environment," from our friends at VeriKwest Systems. Here you'll see an example of how to handle resets and re-generate DUT traffic in UVM without using phase jumping (a UVM feature which is not recommended). While the article uses AXI as the example, the techniques are generally applicable. Next, our friends at Test and Verification Solutions show how to "Increase Verification Productivity with Questa UVM Debug." This article shows you how to take advantage of the UVM-specific debug features built into Questa to maximize your visibility into your UVM testbench.

Now it's time for me to head out to Opening Night. Everyone involved in the production has been working very hard on a very tight schedule to be ready for tonight. It's kind of like tape-out, although admittedly the stakes are maybe not quite as high. And after eight shows through next weekend, they get to start preparing for the next show, which will face many of the same challenges and be on just as tight a budget, with just as tight a schedule. Sound familiar? Break a leg!

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons