by Raghu Ardeishar and Rich Edelman, Verification Technologists, Mentor Graphics
UVM was designed as a means of simplifying and standardizing verification which had been fragmented as a result of many methodologies in use like eRM, VMM, OVM. It started off quite simple. Later on, as a result of feature creep, many of the issues with the older methodologies found its way into UVM. This article looks at some of those issues and suggests ways of simplifying the verification environment.
Why is the UVM becoming so difficult to use? When the UVM was conceived the idea was to take the plethora of existing verification methodologies and create a single one based on the power of SystemVerilog. Good practices from the