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by Amit Kumar Jain, Questa VIP Product Team, Mentor Graphics
ABSTRACT
In a multi-processor system, a cache coherence protocol is vital to maintaining data consistency between local caches and the main memory. With the local processor cache, the bus stimulus must be compliant with the cacheline state in the local cache, and must follow predefined ordering rules between the read/write and cache snoop stimulus. These constraints can make it confusing to generate stimulus on a cache coherent interface. This article addresses such stimulus generation issues by providing easy to use generic APIs along with a cache controller.
INTRODUCTION
The advent of heterogeneous, multi-processor systems with multiple caches sharing the same data has made
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