Cache Coherent Interface Verification IP
In a multi-processor system, a cache coherence protocol is vital to maintain data consistency between local caches and the main memory. With the local processor cache, the bus stimulus must be compliant with the cacheline state following predefined ordering rules between the read/write and cache snoop stimulus. These constraints can make it confusing to generate stimulus. This article addresses such stimulus generation issues by providing easy to use generic APIs along with a cache controller.
Full-access members only
Register your account to view Cache Coherent Interface Verification IP
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.