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by Dr. Mike Bartley, CEO, Suresh Babu, Solutions Architect, and Shyam Ramaswamy, Sales and Business Development Manager, TVS
Debug is one of the major bottlenecks that verification teams face today. Traditionally, to make the debug task easier, significant effort is invested upfront by following standard coding guidelines and writing code that is debug friendly. The near-universal adoption of UVM has, while making the verification process a lot more streamlined, however, increased the debug challenge. While most verification engineers understand how to use the UVM library, in a verification environment, the know-how about the implementation of classes and utilities comprising the UVM library like Factory, Sequencer, Random Sequence
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