Browse all content in Siemens Verification Academy with the tag VA Live

Search Results - 1961 results

Filters

Reset All

Filters

Audience

Beginner (1062)

Intermediate (585)

Advanced (73)

Tags

UVM (530)

SystemVerilog (338)

Verification Horizons (275)

Formal Verification (260)

Testbench (227)

Standards (150)

Verification IP (126)

Debug (122)

Protocol (96)

UVMF (85)

DVCon (83)

UVM Framework (83)

Coverage (80)

UPF (80)

Low Power (79)

RTL (77)

Verification Management (77)

Sequences (74)

Functional Safety (72)

Functional Verification (72)

Clock-Domain Crossing (70)

CDC (69)

FPGA (68)

Assertions (66)

Simulation (66)

FPGA Verification (60)

Verification Planning (59)

Stimulus (56)

Power Aware (55)

Emulation (54)

QDS (54)

Code Example (52)

ISO 26262 (51)

HW/SW Verification (50)

Property Checking (50)

Industry Trends (48)

Verification Trends (48)

Automotive (47)

Integrated Environment (46)

Components (45)

Transactions (45)

Mil/Aero (44)

AI/ML (43)

RDC (43)

Portable Test & Stimulus (42)

Wilson Research Group (42)

Metrics (41)

Formal Apps (40)

Functional Coverage (40)

Constraints (39)

Functional Simulation (39)

Machine Learning (39)

Registers (39)

Analysis (38)

Emerging Trends (38)

UVMC (38)

Verification Process (38)

Formal Coverage (36)

UVM Connect (36)

Coverage Closure (35)

OOP (35)

SystemC (35)

DUT-TB (34)

Trends (34)

AMS (33)

RISC-V (33)

Methodology (32)

SoC (32)

IC/ASIC (31)

Safety Critical (31)

osmosis 2022 (30)

Tests (29)

Avery Verification IP (28)

FPGA Designs (28)

Interfaces (28)

Security Verification (28)

WRG (28)

Bug Hunting (27)

Equivalence Checking (27)

Introduction to UVM (27)

Patterns (27)

Reuse (27)

Connectivity (26)

Properties (26)

Property Checks (26)

Archive (25)

Configuration (25)

Lint (25)

PCIe (25)

UVM Debug (25)

Classes (24)

PCI Express (24)

Reset Issues (24)

Safety Architecture (24)

Scoreboard (24)

UVM Basics (24)

CDC Methodology (23)

Co-Emulation (23)

Cookbook (23)

Objects (23)

Requirements Traceability (23)

Safety Analysis (23)

osmosis 2024 (23)

Design Trends (22)

Fault Campaign (22)

IEEE 1801 (22)

Test Planning (22)

ASIC (21)

Advanced UVM (21)

Factory (21)

Metastability (21)

Non-Trivial Bug Escapes (21)

VHDL (21)

Waveform (21)

osmosis 2023 (21)

Acceleration (20)

Block Level (20)

DO-254 (20)

Hardware Fault (20)

Memory (20)

Power Domain (20)

Reset-Domain Crossing (20)

Synchronization (20)

TLM 2.0 (20)

X-Tracing (20)

Analytics (19)

DAC (19)

Formal Analysis (19)

Functional Verification Study (19)

Object Oriented Programming (19)

Power Management (19)

Python (19)

TLM (19)

Data-driven Verification (18)

FSM (18)

Generative AI (18)

Interactive Mode (18)

Memory Models (18)

Modeling (18)

Proofs (18)

Regression (18)

Artificial Intelligence (17)

Big Data (17)

Code Coverage (17)

Electronic Systems (17)

Fault Injection (17)

Livesim (17)

Object-Oriented Programming in SystemVerilog (17)

QVIP Configurator (17)

Safety Workflow (17)

Verification Efficiency (17)

Advanced Debug Techniques (16)

Assurance (16)

Code Generator (16)

Sequence Driver (16)

Verilog (16)

Asynchronous Clock (15)

Coverage Analysis (15)

Covergroup (15)

Design Constructs (15)

Design Optimization (15)

Inconclusives (15)

Reset-Domain Checking (15)

Verification Practice (15)

ABV (14)

Abstraction (14)

Automotive Functional Safety Forum (14)

COCOTB (14)

Config_db (14)

Coverage Points (14)

Data Types (14)

Driver (14)

Gate-Level (14)

Packages (14)

Sequence Item (14)

Signal (14)

State Space (14)

Verification Productivity (14)

Virtual Sequences (14)

Assertion-Based Verification (13)

Compliance (13)

Constrained Random Verification (13)

Continuous Integration (13)

Customization (13)

Python for Verification Series (13)

Requirements (13)

Requirements Management (13)

SLEC (13)

Sequencer (13)

Subsystem (13)

VRM (13)

Variable (13)

Virtual Interface (13)

X-Propagation (13)

Aerospace (12)

Arrays (12)

Configuration Database (12)

HLS (12)

PSS (12)

Polymorphism (12)

September 2021 - Volume 17 Issue 2 (12)

Unit Testing (12)

Automation (11)

C (11)

Controllers (11)

Coverage Metrics (11)

Creating and Using Constrained Random (11)

Environment Pattern (11)

FPGA Prototyping (11)

Formal Application (11)

Generation (11)

Glitches (11)

High-Speed (11)

Interview (11)

Jenkins (11)

June 2015 - Volume 11 Issue 2 (11)

Methods (11)

Netlist (11)

PYUVM (11)

Processor Design Verification (11)

RDC Design (11)

Reachability Checks (11)

Report (11)

Scenario Generation (11)

U2U (11)

Verification Process Overview (11)

Verification Run Manager (11)

Aerospace and Defense Verification Tech Day (10)

BFMs (10)

Constrained Random Stimulus (10)

Continuous Integration System (10)

Hardware Acceleration (10)

Interrupts (10)

July 2022 - Volume 18 Issue 2 (10)

OVM (10)

Operators (10)

Parameterized Classes (10)

Proof Coverage (10)

Property Debug (10)

Root of Trust (10)

3DIC (9)

ASIL (9)

CDC Analysis (9)

Configuration Object (9)

Coverage Models (9)

Creating and Using Functional Coverage (9)

Curriculum (9)

Data Types and Procedural Statements (9)

Expressions (9)

Failure Analysis (9)

Fault Simulation (9)

Interoperability (9)

June 2018 - Volume 14 Issue 2 (9)

Learning Paths (9)

Reset Architecture (9)

Safety Mechanism (9)

Sequence-Driver Use Models (9)

Siemens Xcelerator Academy (9)

Skill Building (9)

Testbench Automation (9)

Training (9)

UVM Stimulus, Tests, and Regressions (9)

Whats New in Functional Verification (9)

1800.2 (8)

API (8)

Accellera (8)

Adoption Trends (8)

B/C/R Script (8)

Bitstream (8)

Breakpoint (8)

Class Reference (8)

Clock Gating (8)

Collaborative Analysis (8)

Connections (8)

Data Models (8)

Deadlock (8)

Design and Verification IP Forum (8)

Fault Analysis (8)

HTML Docs (8)

Hierarchical Components (8)

Inheritance (8)

March 2021 - Volume 17 Issue 1 (8)

Metrics-Driven (8)

Model Checking (8)

NVMe (8)

OVM2UVM (8)

Productivity Gap (8)

Release (8)

Safety (8)

UCIe (8)

UVM Verification (8)

Universal Chiplet Interconnect Express (8)

VHDL-2008 (8)

Verification IQ (8)

osmosis 2023 A&D (8)

ADAS (7)

CDC Protocol (7)

Chiplets (7)

Class Handles (7)

Class Objects (7)

Clocking Verification Challenges (7)

Connecting the Testbench to the Design (7)

Convergence (7)

Declaration (7)

Design Complexity (7)

Encapsulation (7)

Error Traces (7)

Execution Semantics and Synchronization (7)

Formal Assertion-Based Verification (7)

HPC (7)

IP Blocks (7)

ISA (7)

Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

June 2016 - Volume 12 Issue 2 (7)

Macros (7)

March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Matlab (7)

Messaging (7)

Metastable (7)

Migration (7)

Monitor (7)

Occurrence Property Pattern (7)

Parallel Simulation (7)

Performance (7)

Power Analysis (7)

Power Estimation (7)

Power Logic (7)

Predictive Analysis (7)

Procedural Statements (7)

RDC Violations (7)

Reference Model (7)

Sequential Analysis (7)

Siemens EDA (7)

Simulation Coverage (7)

System Level (7)

Testbench Customization in UVM (7)

U2U Europe (7)

VA Live 2023 - Huntsville (7)

X-Checking (7)

X-Corruption (7)

AXI (6)

Agent (6)

Algorithms (6)

Analog (6)

Appendix (6)

Conditionals (6)

Coverage Intent (6)

DMA Engine (6)

DPI-C (6)

Data Management (6)

December 2022 - Volume 18 Issue 3 (6)

Design Integrity (6)

Design Mitigation (6)

Design for Test (6)

Directed Test (6)

Electronic Hardware (6)

Ethernet (6)

February 2013 - Volume 9 Issue 1 (6)

Hierarchical Flow (6)

IP Security (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MIPI (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Mixed-Signal Verification (6)

Monitors (6)

Multi-die (6)

November 2015 - Volume 11 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

Open Source (6)

Order Property Pattern (6)

PCIe Gen 6 (6)

Power States (6)

Predictors (6)

RDC Analysis (6)

Scalable Verification (6)

Schematic (6)

Schematic Debug (6)

Slave (6)

State Transitions (6)

TLM FIFOS (6)

Testplan (6)

Timing (6)

Verbosity (6)

Voltage Domain Crossing (6)

Waivers (6)

Windows (6)

X-Effects (6)

YAML (6)

osmosis 2024 A&D (6)

AEH (5)

AI Algorithms (5)

Advance Your Verification Methodology (5)

Artificial Neural Network (5)

Backdoor Accesses (5)

Bus Protocol (5)

CXL (5)

Co-Simulation (5)

Command API (5)

Constraint Solver (5)

Creating and Using a Test Plan (5)

DAC 2024 (5)

DDR (5)

DFT (5)

DSP (5)

December 2019 - Volume 15 Issue 3 (5)

Factory Pattern (5)

February 2019 - Volume 15 Issue 1 (5)

Flip-Flop (5)

Gate-Level Simulations (5)

HBM4 (5)

HDL Domain (5)

Hardware Security (5)

Hierarchical Sequences (5)

High-Level Synthesis (5)

Intelligent Automation (5)

Interconnect (5)

Layering (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

March 2018 - Volume 14 Issue 1 (5)

Mixed-Signal Design (5)

Multi-Core Architectures (5)

Non-Determinism (5)

Overrides (5)

PSL (5)

Phasing (5)

Pipelined (5)

Postsim (5)

Power Intent (5)

Processor Core Verification (5)

Randomization (5)

SPI (5)

SVUnit (5)

Safety Metrics (5)

Secure Data Path (5)

Split Transactor (5)

State-Based Model (5)

Structural Analysis (5)

Sub-system Level (5)

Supply Set (5)

Testing Strategies (5)

Tool Assessment (5)

Transaction-Based Acceleration (5)

UVM Forum (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - El Segundo (5)

VA Live 2024 - San Diego (5)

VA Live 2025 - Silicon Valley (5)

VIQ (5)

Verification Component (5)

Wishbone (5)

2.5D (4)

AMBA (4)

Analysis Pattern (4)

Batch and Debug (4)

Bit Width (4)

Black Boxing (4)

CDC Path (4)

Class Types (4)

Concurrent Processes (4)

Coverage Achievement (4)

Design IP (4)

Design Patterns (4)

DisplayPort (4)

Driver Tracing (4)

Dual Domains (4)

ECO (4)

Error (4)

Error Injection (4)

Formal Closure (4)

Formal Testbench (4)

Formal Verification Apps (4)

Functional Correctness (4)

Guidelines (4)

HBM (4)

HDMI (4)

IC Reliability (4)

IEEE (4)

In-Circuit Emulation (4)

June 2017 - Volume 13 Issue 2 (4)

Lifecycle (4)

Mitigation Architecture (4)

Non-Pipelined (4)

November 2018 - Volume 14 Issue 3 (4)

Parameter (4)

Phases (4)

Prototyping (4)

RDC Methodology (4)

Random Faults (4)

Reconvergence (4)

Retention (4)

SVTB (4)

Safety Verification (4)

Simulink (4)

State Machine (4)

Static Checks (4)

Stimulus Pattern (4)

Test Generation (4)

Time Cone (4)

UART (4)

USB (4)

Use Models (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2024 - Huntsville (4)

VA Live 2024 - Westford (4)

VA Live 2025 - El Segundo (4)

Verification Complete (4)

Verification Effectiveness (4)

Verification Success (4)

X-Aware (4)

1.2 (3)

5G (3)

AHB (3)

Affect Probability (3)

Analysis Components (3)

Application Lifecycle Management (3)

Arbitration (3)

Base Test (3)

Bidirectional Protocols (3)

Boolean (3)

CDC Signals (3)

Case Statements (3)

Cause-Effect (3)

Class Variables (3)

Classifications (3)

Clock Propagation (3)

Code Quality (3)

Computational Storage (3)

Compute Express Link (3)

Control Logic (3)

Coroutines (3)

Cover Method (3)

Coverage Exclusion (3)

Cryptography (3)

Data Encryption (3)

Data Link (3)

Data Mining (3)

Data Transfer (3)

Defect Coverage (3)

Delay Loops (3)

Design for Safety (3)

Diagnostic Coverage (3)

Digital Design (3)

Dual Top (3)

Emulatability (3)

Fabric (3)

Fibre Channel (3)

Fork-Join (3)

Golden Model (3)

HDM (3)

Hardware Architecture (3)

Hardware Assurance (3)

Horizontal Reuse (3)

ICE Mode (3)

IP Integration (3)

Implementation Pattern (3)

JEDEC (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

June 2013 - Volume 9 Issue 2 (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

Mailboxes (3)

Mathworks (3)

Memory Debug (3)

NVM Express (3)

Namespaces (3)

NoC (3)

OSCI (3)

Objections (3)

Open Architecture (3)

PCI-SIG (3)

PHY (3)

Parallel Computing (3)

Phase-Level (3)

Power Optimization (3)

Pre-Silicon (3)

Precedence (3)

Protocol Layers (3)

Qrun (3)

Questa Design Solutions (3)

RISC-V Verification Interface (3)

Race Conditions (3)

Radiation Mitigation (3)

Re-Spins (3)

Reset Tree (3)

Routines (3)

Safety Assurance (3)

Security Vulnerabilities (3)

Semaphores (3)

Sequence Library (3)

Sequential Optimization (3)

Slave Agent (3)

Specification Pattern (3)

Spiral Refinement (3)

Static Lists (3)

Strategy (3)

Test Class (3)

Test Environment (3)

Test Realization (3)

Threads (3)

Transaction Recording (3)

Transaction-Level (3)

Type Casting (3)

UALink (3)

UVM Rapid Adoption (3)

Utilization (3)

VIP - 3.1 (3)

VbyOne (3)

Verification Closure (3)

Virtual Methods (3)

Virtual Prototyping (3)

ALU (2)

Abstract Class (2)

Abstract Specification (2)

Abstract Stimulus (2)

Access Path (2)

Agile Development (2)

Airborne Electronic Hardware (2)

Assist (2)

BiQuad (2)

Bidirectional (2)

Bind (2)

CHERI (2)

CSI (2)

CSI-2 (2)

Cache Coherency (2)

Chains (2)

Channel Detection (2)

Checkers (2)

Class Library (2)

Clocking (2)

Concrete Class (2)

Context-Aware Debug (2)

Cost Benefit (2)

Cover Capabilities (2)

Cover Properties (2)

Cover Statement (2)

Coverage Goals (2)

Critical Storage (2)

Cross Coverage (2)

Cross Probing (2)

Cutpoint (2)

DAC 2019 (2)

DVCON 2021 (2)

DVFS (2)

Debug Methodology (2)

Deprecated (2)

Design Assurance (2)

Design Checking (2)

Design Specification (2)

Designers (2)

Determinism (2)

Digital Signal Processing (2)

Digital Twin (2)

Distributed Resource Management (2)

Dynamic Power (2)

ECUs (2)

ED-80 (2)

Enterprise Debug and Analysis (2)

Existence (2)

FIT Rate (2)

FMEDA (2)

FPU (2)

Facial Recognition (2)

Fault Coverage (2)

Fault List (2)

Fault Model (2)

Floating-Point Units (2)

Formal Concepts (2)

Formal Methods (2)

Formal-Based (2)

Front and Back Door (2)

GLS (2)

GOMACTech (2)

HSI (2)

HVL (2)

Hallucination (2)

Handles (2)

Hardware Behavior (2)

Hardware Debugging (2)

Hardware-Assisted Verification (2)

Hole Analysis (2)

Hybrid Virtual Platform (2)

IDE (2)

IEEE 754 (2)

Implies (2)

In-Circuit Simulation (2)

Indexing (2)

Instance (2)

Instance Mapping (2)

Instruction Sets (2)

Integration Level (2)

Integrity Challenges (2)

Interconnect Signals (2)

Intersect (2)

Jittering (2)

LLMs (2)

Large Language Models (2)

Latch-Based Designs (2)

Latches (2)

LockGrab (2)

Logic Cone (2)

Loop Statements (2)

Machine Readable Specification (2)

Makefile (2)

March 2017 - Volume 13 Issue 1 (2)

Memory BIST (2)

Memory-based Sequences (2)

Metric Analyzers (2)

Metric Validation (2)

Observer (2)

OnChip (2)

PCIe Gen 7 (2)

Parallel Compile (2)

Parameterized Tests (2)

Partitioned Compile (2)

Partitioning (2)

Pattern Splitting (2)

Phase Objections (2)

Pin Level (2)

Pipe Interface (2)

Post-silicon Debug (2)

Power Reduction (2)

Probe (2)

Profiling (2)

Proxy Class (2)

QFL (2)

QIS (2)

QoR (2)

Quirky (2)

RTL Emulation (2)

Real Number Modeling (2)

Repair Architecture (2)

Resource Access (2)

Retargeting Flow (2)

SCE-MI (2)

SCSI (2)

SLM (2)

Sampling (2)

Semantics (2)

Sequence API (2)

Sign-Off Methodology (2)

Signal Wait (2)

Silicon Lifecycle Management (2)

Singleton (2)

Specification (2)

Specification-Driven Methodology (2)

Static Analyses (2)

Static Properties (2)

Stimulus Generation (2)

Structural Checks (2)

Structures (2)

Successive Refinement (2)

Supply Chain (2)

System Analysis (2)

System-in-Package (2)

TBX (2)

Tcl/Tk (2)

Test Compression (2)

Test Coverage (2)

Test Flow (2)

Testbench Architecture (2)

Thread Control (2)

Throughout (2)

Transaction Layer (2)

UCIe 2.0 (2)

UEC (2)

USB4 (2)

UVM Simulation (2)

UVVM (2)

Unidirectional (2)

Universal Approximation (2)

Unreachability (2)

Until (2)

VPI (2)

Vectors (2)

Verification Crisis (2)

Verification Cycles (2)

Vertical Reuse (2)

Virtual Method (2)

Virtual Sequencers (2)

Virtualization (2)

Visualization (2)

X-Mitigation (2)

X-Pessimism (2)

X-State (2)

$display (1)

3PIP (1)

ACE (1)

AI Model (1)

APB (1)

API Sequences (1)

ASIP (1)

Absence (1)

Active Driver Tracing (1)

Address Mapping (1)

Address Space Management (1)

Alternate Routing ID (1)

Analysis Port (1)

Antecedent (1)

Architectural Verification (1)

Arithmetic (1)

Autonomous Systems (1)

Autonomous Vehicles (1)

BIST (1)

Back Pointers (1)

Backward Compatibility (1)

Barriers (1)

Base Entity (1)

Behavioral Coverage (1)

Benchmarks (1)

Bins (1)

Block to Chip (1)

Bounded Model Checking (1)

Bounded Proof (1)

Break on Change (1)

Build Flow (1)

Build Phase (1)

Built-In Self-Test (1)

Bus Agent (1)

Bus Functional Models (1)

C-PHY (1)

CDMA (1)

CMA (1)

COMRESET (1)

COTS (1)

CPF (1)

CPU Model (1)

CSD (1)

Cache Predictor (1)

Callbacks (1)

Certification (1)

Checkpoint (1)

Class Connections (1)

Clock Cycle (1)

Cloud Computing (1)

Cloud-Based Environment (1)

Command Line Processor (1)

Component Measurement and Authentication (1)

Cone of Influence (1)

Connected Verification (1)

Consequent (1)

Control Paths (1)

Conversion (1)

Convolutional Neural Networks (1)

Counterexample (1)

Cover Property (1)

Coverage Holes (1)

Coverage Matrix (1)

Crystal3 (1)

D-PHY (1)

DSI (1)

DVCon 2024 (1)

DVCon 2025 (1)

DVI (1)

Data Corruption (1)

Data Processing (1)

Datapath (1)

December 2017 - Volume 13 Issue 3 (1)

Declarative Environment (1)

Design Analysis (1)

Design Constraints (1)

Design Cycle (1)

Design Solutions (1)

Design Under Test (1)

Design.bin (1)

Deterministic Test (1)

Development Environment (1)

Do-Methods (1)

Domain Specific Architectures (1)

Domain Topologies (1)

Dynamic CDC (1)

EMC (1)

Elliptic Curve (1)

Embedded Analytics (1)

Embedded Software (1)

End of Test (1)

Enumeration (1)

Execution Trace (1)

FMEA (1)

FMU (1)

Fault Detection (1)

Fault Grading (1)

Field Macros (1)

Flash (1)

Flow Control (1)

Follows (1)

Formal Directives (1)

Formal Test Planning (1)

Forum (1)

Full Prove (1)

Functional Blocks (1)

Functional Monitoring (1)

GPU (1)

HAV (1)

HDCP (1)

HYCON (1)

Hardening (1)

High-Frequency Trading (1)

Host Processor (1)

IC Design (1)

IEC 62304 (1)

IEEE 1800-2023 (1)

IP Quality (1)

ISO 21434 (1)

ISO 21448 (1)

Illegal Bins (1)

Implementation Driven Formal (1)

Implicit/Explicit (1)

In-System Test (1)

Isolation (1)

Iterations (1)

JTAG (1)

Japanese (1)

June 2012 - Volume 8 Issue 2 (1)

June 2014 - Volume 10 Issue 2 (1)

LPDDR6 (1)

LRM (1)

LSF (1)

LSTM (1)

Lane Margining (1)

Leads-To (1)

Livelock (1)

Load/Store APIs (1)

Lockstep (1)

Logic Faults (1)

Low Latency (1)

Lump Sum Build (1)

MBIST (1)

MBSE (1)

MCPs (1)

MUX (1)

March 2016 - Volume 12 Issue 1 (1)

Memory Stimulus (1)

Model Generator (1)

Model Structure (1)

Model-Based Design (1)

Modules (1)

Multi-Cycle Paths (1)

NLP (1)

Not Recommended (1)

November 2016 - Volume 12 Issue 3 (1)

OSVVM (1)

OVL (1)

Objective CD-10 (1)

Occurrence (1)

Open Verification Library (1)

Optical Network (1)

Order (1)

PAM4 (1)

PCIe Gen 4 (1)

PCie Gen 5 (1)

PDU (1)

PSS 3.0 (1)

Package Organization (1)

Parameter Checkers (1)

Params Package (1)

Pattern Generation (1)

Phase Sequences (1)

Plusargs (1)

Point-to-Point Connections (1)

Power Architecture (1)

Power Efficiency (1)

Pre-Condition (1)

Priority (1)

Process Node (1)

Processing Elements (1)

Programmable Logic (1)

Property Analysis (1)

Property Editor (1)

Protocol Agent (1)

Protocol Checkers (1)

Proxy-Driven (1)

QOS Processor (1)

RAM (1)

RDMA (1)

Read Completion Boundary (1)

Receiver (1)

Recording (1)

Recurrent Neural Networks (1)

Reset Handling (1)

Show Less

April 2025

Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity
Verification IP Apr 30, 2025 Kevin Ham Webinar
Securing your FPGA Design from RTL through to the Bitstream
FPGA Verification Apr 23, 2025 Keerthi Devraj Webinar
Faster Debug Using QuestaSim Interactive Coverage Analysis
Simulation Apr 16, 2025 Justin Royse Webinar
Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator
Verification IQ Apr 03, 2025 Mark Carey Webinar

March 2025

Accelerating Innovation: PCIe Gen7 Verification for High-Speed Designs
Verification IP Mar 26, 2025 Jalaj Gupta Webinar
Accellera announces fee-free availability of IEEE Std. 1801™-2024
Standards Mar 19, 2025 Dennis Brophy link
Safety Analysis for Automotive Chips Based on ISO 26262
Functional Safety Mar 12, 2025 Jyothy M Jaganathan pdf
Safety Analysis for Automotive Chips Based on ISO 26262
Functional Safety Mar 12, 2025 Jyothy M Jaganathan Webinar
GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation
Simulation Mar 10, 2025 Joe Hupcey link
Faster Debug of Complex Testbenches using Visualizer
Debug Mar 05, 2025 Erik Jessen Webinar
Faster Debug of Complex Testbenches Using Visualizer
Debug Mar 05, 2025 Erik Jessen pdf
GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking
FPGA Verification Mar 04, 2025 Joe Hupcey link

February 2025

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
FPGA Verification Feb 19, 2025 Kevin Urish pdf
Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream
FPGA Verification Feb 19, 2025 Kevin Urish Webinar
IC/ASIC Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Paper
FPGA Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Paper
2024 Siemens EDA and Wilson Research Group Functional Verification Study: 7-Part Video Series
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Track
Introduction and Study Background
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
IC/ASIC Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster pdf
FPGA Functional Verification Trend Report - 2024
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster pdf
Verification Effectiveness Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Verification Effort Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Design Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Language and Methodology Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session
Verification Technology Trends
Planning, Measurement and Analysis Feb 17, 2025 Harry Foster Session

PCIe Gen7 Webinar

Wednesday, Mar 26th-10:00 AM PDT

Accelerating Innovation: PCIe Gen7 Verification for High-Speed Designs

Debug Webinar

Thursday, Apr 03rd-8:00 AM PDT

Accelerate Root Cause Analysis & Reduce Debug Turnaround Time with Questa VIQ Regression Navigator

Simulation Webinar

Wednesday, Apr 16th-8:00 AM PDT

Faster Debug Using QuestaSim Interactive Coverage Analysis

FPGA Design Webinar

Wednesday, Apr 23rd-8:00 AM PDT

Securing your FPGA Design from RTL through to the Bitstream

Avery VIP Webinar

Wednesday, Apr 30th-10:00 AM PDT

Ethernet 1.6T, Infiniband, UALink & UEC Verification for Next-Gen Connectivity

Browse all content in Siemens Verification Academy with the tag VA Live - Westford

Search Results - 1961 results

Filters

April 2025

March 2025

February 2025