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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

June 2017 - Volume 13 Issue 2 (11)

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July 2022 - Volume 18 Issue 2 (10)

June 2013 - Volume 9 Issue 2 (10)

LLMs (10)

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1800.2 (9)

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AI Model (9)

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Curriculum (9)

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June 2012 - Volume 8 Issue 2 (9)

June 2014 - Volume 10 Issue 2 (9)

June 2018 - Volume 14 Issue 2 (9)

Learning Paths (9)

Metastable (9)

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Siemens Xcelerator Academy (9)

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VHDL 2008 (9)

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DMA Engine (8)

Design and Verification IP Forum (8)

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Factory Pattern (8)

February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

Guidelines (8)

HTML Docs (8)

June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

OSCI (8)

OVM2UVM (8)

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Release (8)

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UCIe 2.0 (8)

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Verification Complete (8)

Voltage Domain Crossing (8)

Windows (8)

Wishbone (8)

XML (8)

osmosis 2023 A&D (8)

ADAS (7)

Adaptive (7)

Base Class (7)

Bind (7)

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C++ (7)

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Clocking Verification Challenges (7)

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Connecting the Testbench to the Design (7)

Context-Aware Debug (7)

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Design Constraints (7)

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Error Injection (7)

Execution Semantics and Synchronization (7)

Fabric (7)

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Fork-Join (7)

IP Integration (7)

IP Security (7)

ISA (7)

Instance (7)

Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

Layering (7)

MBIST (7)

MCPs (7)

March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

Non-Determinism (7)

November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Order Property Pattern (7)

Parameterized Tests (7)

Post-silicon Debug (7)

Power Estimation (7)

Predictors (7)

Property Analysis (7)

Safety Verification (7)

Sequential Analysis (7)

Siemens EDA (7)

Supply Network (7)

Syntax (7)

Test Generation (7)

Testbench Customization in UVM (7)

Tool Qualification (7)

UVVM (7)

Unified Coverage Database (7)

VA Live 2023 - Huntsville (7)

Verbosity (7)

Verification Models (7)

Verification Quality (7)

X-Effects (7)

AEH (6)

Address Mapping (6)

Appendix (6)

Artificial Neural Network (6)

Behavioral Modeling (6)

Bugged Out Podcast (6)

Bus Functional Models (6)

Clock Propagation (6)

Concurrent Processes (6)

Coverage Holes (6)

Coverage Intent (6)

Creating and Using a Test Plan (6)

DAC 2018 (6)

December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Defect Coverage (6)

Design Completion (6)

Design Mitigation (6)

Design Patterns (6)

Design Scaling (6)

Development Environment (6)

Distributed Resource Management (6)

Dual Domains (6)

Dynamic Power (6)

Electronic Hardware (6)

Flip-Flop (6)

Front and Back Door (6)

HDM (6)

HVL (6)

Hardware Designs (6)

Hardware-Assisted Verification (6)

Hierarchical Data Model (6)

Implicit/Explicit (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

Phases (6)

Power Efficiency (6)

Pre-Silicon (6)

Precedence (6)

Random Faults (6)

Respins (6)

Semiconductor (6)

Sequence Library (6)

Split Transactor (6)

Static Analyses (6)

Static RDC (6)

Stimulus Free Verification (6)

Tessent Test Solutions (6)

UCIe 3.0 (6)

UVM Forum (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VA Live 2026 - Hudson (6)

VHDL Testbench (6)

Verification Cycles (6)

Verification Workflow (6)

Virtual Prototyping (6)

Visualization (6)

YAML (6)

osmosis 2024 A&D (6)

Advance Your Verification Methodology (5)

Agile Development (5)

Analysis Pattern (5)

Analysis Port (5)

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Argument (5)

BIST (5)

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CHERI (5)

CXL (5)

Checkpoint (5)

Class Library (5)

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Constraint Solver (5)

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Converters (5)

Coverpoint (5)

DAC 2024 (5)

DSP (5)

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Debug Challenges (5)

December 2019 - Volume 15 Issue 3 (5)

Design Cycle (5)

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Domain Specific Architectures (5)

Driver Tracing (5)

Dual Top (5)

Error (5)

Exhaustive (5)

FMEDA (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Methods (5)

Formal Testbench (5)

Function (5)

HBM (5)

HBM4 (5)

Hardware Verification (5)

High-Speed (5)

IDE (5)

IP Blocks (5)

In-Circuit Emulation (5)

Integration Level (5)

JEDEC (5)

LRM (5)

Low Latency (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

Memory-Mapped Registers (5)

Metastability Injection (5)

Model Context Protocol (5)

NVM Express (5)

Namespaces (5)

Non-Pipelined (5)

Non-Reset (5)

Partitioning (5)

Processor Core Verification (5)

Quirky (5)

Repository (5)

Reset Signal (5)

SFV (5)

SSD (5)

SVTB (5)

SVUnit (5)

Simulink (5)

State-Based Model (5)

Stimulus Pattern (5)

Test Coverage (5)

Transaction-Based Acceleration (5)

UART (5)

UVC (5)

Unreachability (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

VA Live 2026 - El Segundo (5)

Verbose (5)

Verification Case Document (5)

Verification Success (5)

Virtual Methods (5)

X-Aware (5)

X-Mitigation (5)

5G (4)

AHB (4)

AMS Engines (4)

AMS Simulation (4)

BISR (4)

Bandwidth (4)

Batch and Debug (4)

Bi-Directional (4)

Bit Width (4)

Boolean (4)

Bounded Model Checking (4)

Case Statements (4)

Class Variables (4)

Classifications (4)

Coverage Achievement (4)

DVFS (4)

Data Link (4)

Data Processing (4)

Deprecated (4)

Design Analysis (4)

Design Creation (4)

Design Specification (4)

Determinism (4)

Digital Domain (4)

DisplayPort (4)

Domain Configuration (4)

ECO (4)

ED-80 (4)

ENV Package (4)

Enumeration (4)

Equivalent RTL (4)

Fault Coverage (4)

Fault Detection (4)

Fault List (4)

Fibre Channel (4)

Formal Closure (4)

GPU (4)

HDMI (4)

Hybrid Virtual Platform (4)

IC Design (4)

ICE Mode (4)

IEEE (4)

Implementation Driven Formal (4)

Implementation Pattern (4)

In-Circuit Simulation (4)

In-System Test (4)

Initial States (4)

Instantiate (4)

LFM (4)

Language Constructs (4)

Large Language Models (4)

Mathworks (4)

Mitigation Architecture (4)

Monitor (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

PHY (4)

Parallel Compile (4)

Phase Objections (4)

Plusargs (4)

Power Constraints (4)

Protocol Checkers (4)

Proxy Class (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

Race Conditions (4)

Reconfiguration (4)

Reset Handling (4)

Retargeting Flow (4)

Risk Mitigation (4)

Semantics (4)

Sequential Logic (4)

Specification Pattern (4)

Static Timing (4)

Stream (4)

Structural Checks (4)

Subscriber (4)

Synchronizer (4)

Synergistic Verification (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Toolkit (4)

Top Down (4)

Transactors (4)

Trust Verification (4)

UCIS (4)

UEC (4)

UPF 3.0 (4)

UPF 4.0 (4)

USB (4)

UVM 1.1d (4)

UVM 1.2 (4)

UVM Monitor (4)

Unidirectional (4)

Utilization (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

VPM (4)

Vectors (4)

Verification Blueprint (4)

Verification Maturity (4)

Virtual Sequencers (4)

$display (3)

1.2 (3)

AMS Verification (3)

APB3 (3)

Abstract Class (3)

Abstract-Concrete (3)

Access Path (3)

Affect Probability (3)

Airborne Electronic Hardware (3)

Analysis Components (3)

Application Lifecycle Management (3)

Autonomous Systems (3)

Autonomous Vehicles (3)

Base Test (3)

BiQuad (3)

Bias (3)

Bidirectional Protocols (3)

Block Diagram (3)

Build Process (3)

Built-In Self-Test (3)

CDC Signals (3)

CSI-2 (3)

Cause-Effect (3)

Certification (3)

Clock Definitions (3)

Clock Detection (3)

Clocking (3)

Code Quality (3)

Command Line Processor (3)

Connect Phase (3)

Controllability (3)

Coroutines (3)

Cover Method (3)

Coverage Data (3)

Coverage Exclusion (3)

Critical Storage (3)

Cross-Domain (3)

Cryptography (3)

Cutpoint (3)

DFT Architecture (3)

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Delay Loops (3)

Design Under Test (3)

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Designers (3)

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ESL (3)

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FWHW (3)

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Golden Model (3)

HLV (3)

Hardware Architecture (3)

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Horizontal Reuse (3)

Illegal Bins (3)

Integrity Challenges (3)

Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

Lane Margining (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

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MC2 (3)

MUX (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

Method (3)

NRRs (3)

NoC (3)

OSVVM (3)

Observer (3)

Open Architecture (3)

PCI-SIG (3)

PCIe Gen 8 (3)

Package Organization (3)

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Phase-Level (3)

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Power Architecture (3)

Power Gating (3)

Protocol Layers (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

RTL Model (3)

Radiation Mitigation (3)

Re-targeting (3)

Real Number Modeling (3)

Resource Utilization (3)

Retimers (3)

Routines (3)

SDC (3)

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Safety Assurance (3)

Security Coverage (3)

Security Vulnerabilities (3)

Semaphores (3)

Sequential Optimization (3)

Serial Interface (3)

Shift Left (3)

Sign-Off Methodology (3)

Signal Property (3)

Signal-Level (3)

Silicon Lifecycle Management (3)

Single Step Debug (3)

Singleton (3)

Slave Agent (3)

Soft Reset (3)

Source Code Management (3)

Specification Driven Formal (3)

Spiral Refinement (3)

State Transition (3)

Static Lists (3)

Static Properties (3)

Subsystem (3)

System Verification (3)

TBX (3)

TDISP (3)

Task Call (3)

Test Realization (3)

Timing Analysis (3)

Timing Integrity (3)

Tool Optimization (3)

Transaction Layer (3)

Transfer Protocols (3)

Transitive (3)

Type Casting (3)

Typedef (3)

UEFI (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

Unreachable Code (3)

VHDL-2019 (3)

VIP - 3.1 (3)

Values (3)

VbyOne (3)

Verification Bottleneck (3)

Verification Framework (3)

Verification Integrity (3)

View Modes (3)

Wave Window (3)

Wrapper (3)

X-State (3)

2D/3D (2)

AHB-Lite (2)

AI Accelerator (2)

AI-Assisted (2)

ALU (2)

ARBM (2)

Abstract Specification (2)

Abstract Stimulus (2)

Architectural Verification (2)

Arithmetic (2)

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August 2012

Functional Coverage
FPGA Verification Aug 30, 2012 Ray Salemi Session

June 2012

Using the UVM Register Layer
UVM - Universal Verification Methodology Jun 22, 2012 John Aynsley pdf
Siemens EDA has Accellera's Latest Standard Covered
Coverage Jun 15, 2012 Darron May Article
Is Intelligent Testbench Automation For You?
Portable Stimulus Jun 15, 2012 Mark Olen Article
Automated Generation of Functional Coverage Metrics for Input Stimulus
Portable Stimulus Jun 15, 2012 Mike Andrews - Siemens Eda Article
Targeting Internal-State Scenarios in an Uncertain World
Portable Stimulus Jun 15, 2012 Matthew Ballance Article
Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces
Acceleration Jun 15, 2012 Jim Kenney - Siemens Eda Article
On the Fly Reset
UVM - Universal Verification Methodology Jun 15, 2012 Mark Peryer Article
Relieving the Parameterized Coverage Headache
Coverage Jun 15, 2012 Bryan Ramirez Article
Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
FPGA Verification Jun 15, 2012 Stephan Van Beek, Sudhir Sharma, Sudeepa Prakash - Mathworks Article
Better Living Through Better Class-Based SystemVerilog Debug
SystemVerilog Jun 15, 2012 Rich Edelman Article
Verification Horizons - Volume 8, Issue 2
Standards Jun 15, 2012 Tom Fitzpatrick pdf
AMS Design Configuration Schemes
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Track
Overview to AMS Configuration
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Session
Introduction to Metrics
Planning, Measurement and Analysis Jun 01, 2012 Harry Foster Session
Analog/Mixed-Signal Domain
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Session
The Driving Forces for Change
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
Design Methodologies
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Session
Design Topologies
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Session
What Can Metrics Tell Us?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
Mixing Languages
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Session
What's Needed to Address the Problem?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
Questa ADMS: AMS Configuration
Analog Mixed-Signal Verification Jun 01, 2012 Ahmed Eisawy Session
What's Needed to Adopt Metrics?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
Evolving Trends in Functional Verification
Planning, Measurement and Analysis Jun 01, 2012 Harry Foster pdf