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September 2021 - Volume 17 Issue 2 (12)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

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March 2021 - Volume 17 Issue 1 (8)

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July 2020 - Volume 16 Issue 2 (7)

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November 2014 - Volume 10 Issue 3 (7)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

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March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

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Transaction-Level (6)

UCIe 3.0 (6)

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VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

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VHDL Testbench (6)

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December 2019 - Volume 15 Issue 3 (5)

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February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

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March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

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Unified Coverage Database (5)

VA Live 2019 - Westford (5)

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November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

Partitioning (4)

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UART (4)

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UPF 4.0 (4)

USB (4)

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VA Live 2023 - Austin (4)

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VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

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1.2 (3)

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JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

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UVM 1.1d (3)

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February 2013

SVA in a UVM Class-based Environment
SystemVerilog Feb 25, 2013 Ben Cohen Article
The Formal Verification of Design Constraints
Formal Verification Feb 25, 2013 Ajay Daga - Fishtail Design Automation Article
OVM to UVM Migration, or There and Back Again: A Consultant’s Tale
UVM - Universal Verification Methodology Feb 25, 2013 Mark Litterick - Verilab Gmbh Article
Verification Horizons - Volume 9, Issue 1
Standards Feb 01, 2013 Tom Fitzpatrick pdf

January 2013

Improve AMS Verification Quality
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Extend Structured Formal Verification to AMS
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Extend Power-Aware Verification to AMS
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Analog Aspects in AMS
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Overview to Improve AMS Quality
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Design Configuration Schemes
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Mixing Languages
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Design Topologies
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Design Methodologies
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Analog/Mixed-Signal Domain
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Overview to AMS Configuration
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Improve AMS Verification Performance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Modeling Guidance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Modeling Abstraction
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Engines
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Overview to Improve AMS Performance
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
VHDL-2008 Overview
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Testbench Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
RTL Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Operator Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Package Type Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session