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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

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July 2022 - Volume 18 Issue 2 (10)

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June 2012 - Volume 8 Issue 2 (9)

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June 2018 - Volume 14 Issue 2 (9)

Learning Paths (9)

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Whats New in Functional Verification (9)

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DMA Engine (8)

Design and Verification IP Forum (8)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

HDL Domain (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

Messaging (8)

Mixed-Signal Design (8)

OSCI (8)

OVM2UVM (8)

Occurrence Property Pattern (8)

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Postsim (8)

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Release (8)

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Supply Set (8)

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UCIe 2.0 (8)

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Voltage Domain Crossing (8)

osmosis 2023 A&D (8)

ADAS (7)

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Bind (7)

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ISA (7)

Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

LLMs (7)

Layering (7)

March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

Modules (7)

Monitor (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

Order Property Pattern (7)

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Supply Network (7)

TLM FIFOS (7)

Technology Scaling (7)

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Testbench Customization in UVM (7)

Tool Qualification (7)

Transaction Recording (7)

VA Live 2023 - Huntsville (7)

Verification Complete (7)

XML (7)

AEH (6)

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Appendix (6)

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Class Types (6)

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Coverage Intent (6)

Creating and Using a Test Plan (6)

DAC 2018 (6)

DDR (6)

Debug Methodology (6)

December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Design Constraints (6)

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Design Patterns (6)

Development Environment (6)

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Electronic Hardware (6)

Fabric (6)

Flip-Flop (6)

Front and Back Door (6)

HDL (6)

HDM (6)

Hardware Designs (6)

Hierarchical Flow (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MBIST (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

Power Efficiency (6)

Pre-Silicon (6)

Prototyping (6)

Random Faults (6)

Respins (6)

Slave (6)

Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

Verbosity (6)

Verification Effectiveness (6)

Visualization (6)

Windows (6)

X-Effects (6)

YAML (6)

osmosis 2024 A&D (6)

AI Model (5)

ATPG (5)

Adaptive (5)

Advance Your Verification Methodology (5)

Agile Development (5)

Analysis Pattern (5)

BIST (5)

Base Class (5)

Bus Functional Models (5)

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CHERI (5)

Callbacks (5)

Checkpoint (5)

Class Library (5)

Clock Propagation (5)

Co-Verification (5)

Concurrent Processes (5)

Constraint Solver (5)

Control Logic (5)

Converters (5)

Coverage Holes (5)

DAC 2024 (5)

DSP (5)

Data Encryption (5)

December 2019 - Volume 15 Issue 3 (5)

Defect Coverage (5)

Design Scaling (5)

Dual Domains (5)

Error (5)

FMEDA (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

HBM4 (5)

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Hardware-Assisted Verification (5)

Hierarchical Data Model (5)

High-Speed (5)

IDE (5)

Implicit/Explicit (5)

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Instance (5)

JEDEC (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

NVM Express (5)

Namespaces (5)

Post-silicon Debug (5)

Precedence (5)

Processor Core Verification (5)

Quirky (5)

Repository (5)

SSD (5)

SVUnit (5)

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Simulink (5)

Spice (5)

Split Transactor (5)

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Static RDC (5)

Stimulus Free Verification (5)

Stimulus Pattern (5)

Tessent Test Solutions (5)

Test Class (5)

Threads (5)

Transaction-Based Acceleration (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

VA Live 2026 - El Segundo (5)

Verbose (5)

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5G (4)

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Batch and Debug (4)

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Bins (4)

Bit Width (4)

Black Boxing (4)

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C++ (4)

CXL (4)

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Context-Aware Debug (4)

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DVFS (4)

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Deprecated (4)

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DisplayPort (4)

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ECO (4)

ED-80 (4)

Enumeration (4)

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HBM (4)

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IC Design (4)

ICE Mode (4)

IEEE (4)

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Initial States (4)

LFM (4)

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Low Latency (4)

MCPs (4)

Mathworks (4)

Metastability Injection (4)

Mitigation Architecture (4)

Non-Pipelined (4)

Non-Reset (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

Partitioning (4)

Phase Objections (4)

Phases (4)

Plusargs (4)

Protocol Checkers (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

Race Conditions (4)

Reset Handling (4)

Reset Signal (4)

Risk Mitigation (4)

Root Cause (4)

SFV (4)

SVTB (4)

Specification Pattern (4)

Structural Checks (4)

Subscriber (4)

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Synergistic Verification (4)

Syntax (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Time-to-Market (4)

Trust Verification (4)

UART (4)

UEC (4)

UPF 4.0 (4)

USB (4)

Unified Coverage Database (4)

Unreachability (4)

Use Models (4)

Utilization (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

Vectors (4)

Verification Models (4)

Verification Success (4)

X-Aware (4)

$display (3)

1.2 (3)

AHB (3)

Affect Probability (3)

Agentic AI Framework (3)

Airborne Electronic Hardware (3)

Analysis Components (3)

Analysis Port (3)

Application Lifecycle Management (3)

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Autonomous Systems (3)

BISR (3)

Base Test (3)

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Boolean (3)

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Built-In Self-Test (3)

CDC Signals (3)

CSI-2 (3)

Case Statements (3)

Cause-Effect (3)

Certification (3)

Class Variables (3)

Classifications (3)

Clocking (3)

Code Quality (3)

Coroutines (3)

Cover Method (3)

Coverage Exclusion (3)

Cryptography (3)

Data Processing (3)

Delay Loops (3)

Design Cycle (3)

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Design for Safety (3)

Domain Specific Architectures (3)

Dual Top (3)

ESL (3)

Emulatability (3)

Exhaustive (3)

FWHW (3)

Fault Detection (3)

Fibre Channel (3)

Formal Verification Apps (3)

Golden Model (3)

HLV (3)

Handles (3)

Hardware Architecture (3)

Hardware Assurance (3)

Horizontal Reuse (3)

Integrity Challenges (3)

Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

NRRs (3)

NoC (3)

OSVVM (3)

Observer (3)

Open Architecture (3)

PCI-SIG (3)

PHY (3)

Parallel Compile (3)

Parallel Computing (3)

Phase-Level (3)

Polymorphic Behavior (3)

Power Architecture (3)

Power Gating (3)

Profiling (3)

Protocol Layers (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

Radiation Mitigation (3)

Re-Spins (3)

Re-targeting (3)

Real Number Modeling (3)

Reconfiguration (3)

Resource Utilization (3)

Routines (3)

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Semantics (3)

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Semiconductor (3)

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Serial Interface (3)

Shift Left (3)

Singleton (3)

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Source Code Management (3)

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State Transition (3)

Static Lists (3)

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Stream (3)

TBX (3)

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Test Coverage (3)

Test Realization (3)

Tool Optimization (3)

Toolkit (3)

Transfer Protocols (3)

Transitive (3)

Type Casting (3)

UEFI (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

Unidirectional (3)

Unreachable Code (3)

VHDL-2019 (3)

VIP - 3.1 (3)

VbyOne (3)

Verification Cycles (3)

Verification Framework (3)

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Virtual Prototyping (3)

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X-State (3)

2D/3D (2)

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ALU (2)

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ASIL-C (2)

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BiQuad (2)

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CDC Working Group (2)

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CSI (2)

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DVCON 2021 (2)

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Dead Code (2)

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ECUs (2)

ENV Package (2)

Elements List (2)

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False Path (2)

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Floating-Point Hardware (2)

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Governance (2)

Graph-Based Stimulus (2)

HSI (2)

HVL (2)

Hallucination (2)

Hardening (2)

Hardware / Software (2)

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Hardware Debugging (2)

Heterogeneous (2)

Hole Analysis (2)

Hybrid Virtual Platform (2)

IEEE 754 (2)

IP-XACT (2)

Illegal Bins (2)

Implies (2)

Indexing (2)

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Instantiate (2)

Instruction Sets (2)

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Intersect (2)

JTAG (2)

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LVS (2)

Last Mile Problem (2)

Latch-Based Designs (2)

Latches (2)

Leakage (2)

Liberty Syntax (2)

LockGrab (2)

Lockstep (2)

Logic Cone (2)

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December 2013

System Level Functional Coverage Example
Coverage Dec 04, 2013 Harry Foster Chapter
APB3 Protocol Monitor
Coverage Dec 04, 2013 Harry Foster Chapter
Design For Analysis
Coverage Dec 04, 2013 Harry Foster Chapter
Coverage Cookbook
Coverage Dec 04, 2013 Harry Foster pdf

October 2013

Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation
UVM - Universal Verification Methodology Oct 18, 2013 Tom Fitzpatrick Webinar
Abstract Concrete (.tgz)
UVM - Universal Verification Methodology Oct 07, 2013 tar
Generation_seq_persistence.tgz
Standards Oct 07, 2013 tar
Generation_seq_rand.tgz
Standards Oct 07, 2013 tar
Interrupts_parallel_processing.tgz
Standards Oct 07, 2013 tar
Interrupts_prioritised.tgz
Standards Oct 07, 2013 tar
Interrupts_simple.tgz
Standards Oct 07, 2013 tar
Overriding.tgz
Standards Oct 07, 2013 tar
Priority_arbitration.tgz
Standards Oct 07, 2013 tar
Priority_grab_lock.tgz
Standards Oct 07, 2013 tar
QVIP Express (.tgz)
UVM - Universal Verification Methodology Oct 07, 2013 tar
Tb_build_ss_tb.tgz
Standards Oct 07, 2013 tar
Use_models_bidir_get_put_uvm.tgz
Standards Oct 07, 2013 tar
Use_models_bidir_item_done_uvm.tgz
Standards Oct 07, 2013 tar
Bidirectional Sequence Driver Use Model (.tgz)
UVM - Universal Verification Methodology Oct 07, 2013 Verification Methodology Team tar
Use_models_pipelined_get_put.tgz
Standards Oct 07, 2013 tar
Use_models_pipelined_item_done.tgz
Standards Oct 07, 2013 tar
Use_models_tb_build_tbx_uvm.tgz
Standards Oct 07, 2013 tar
Use_models_unidirectional.tgz
Standards Oct 07, 2013 tar
Uvm_Abstract-concrete.tgz
Standards Oct 07, 2013 tar
Uvm_generation_seq_persistence.tgz
Standards Oct 07, 2013 tar

Agentic AI Webinar

Wednesday, Apr 22nd-8:00 AM PDT

From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

Press Release

Siemens accelerates integrated circuit design and verification with agentic AI in Questa One

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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December 2013

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