Browse all content in Siemens Verification Academy with the tag verification trends

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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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July 2022 - Volume 18 Issue 2 (10)

June 2013 - Volume 9 Issue 2 (10)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

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Fabric (7)

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GPU (7)

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ISA (7)

Instance (7)

Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

Layering (7)

MCPs (7)

March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

Non-Determinism (7)

November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Order Property Pattern (7)

Parameterized Tests (7)

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Predictors (7)

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Siemens EDA (7)

Supply Network (7)

Syntax (7)

Testbench Customization in UVM (7)

Tool Qualification (7)

UVVM (7)

Unified Coverage Database (7)

VA Live 2023 - Huntsville (7)

Verbosity (7)

Verification Models (7)

Verification Quality (7)

Verification Workflow (7)

X-Effects (7)

AEH (6)

Address Mapping (6)

Appendix (6)

Artificial Neural Network (6)

Bandwidth (6)

Bugged Out Podcast (6)

Clock Propagation (6)

Concurrent Processes (6)

Coverage Holes (6)

Coverage Intent (6)

Coverpoint (6)

Creating and Using a Test Plan (6)

DAC 2018 (6)

Data Link (6)

December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Defect Coverage (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

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Open Source (6)

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Static RDC (6)

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Tessent Test Solutions (6)

Transactors (6)

USB (6)

UVM Forum (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VA Live 2026 - Hudson (6)

VHDL Testbench (6)

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YAML (6)

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Advance Your Verification Methodology (5)

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Constraint Solver (5)

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DAC 2024 (5)

DSP (5)

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Debug Challenges (5)

December 2019 - Volume 15 Issue 3 (5)

Design Creation (5)

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Domain Specific Architectures (5)

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Error (5)

Exhaustive (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Methods (5)

Formal Testbench (5)

Function (5)

HBM (5)

HBM4 (5)

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High-Speed (5)

IDE (5)

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JEDEC (5)

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Low Latency (5)

Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

Memory-Mapped Registers (5)

Metastability Injection (5)

Model Context Protocol (5)

Multi-Language Environment (5)

NVM Express (5)

Namespaces (5)

Non-Pipelined (5)

Non-Reset (5)

PCIe Gen 8 (5)

Partitioning (5)

Processor Core Verification (5)

Quirky (5)

RTL Model (5)

Repository (5)

Reset Signal (5)

SFV (5)

SSD (5)

SVTB (5)

SVUnit (5)

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Shift Left (5)

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State-Based Model (5)

Stimulus Pattern (5)

Test Coverage (5)

Transaction-Based Acceleration (5)

UART (5)

UVC (5)

Unreachability (5)

VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

VA Live 2024 - Huntsville (5)

VA Live 2024 - Westford (5)

VA Live 2025 - Silicon Valley (5)

VA Live 2026 - El Segundo (5)

Verbose (5)

Verification Case Document (5)

Verification Success (5)

Virtual Methods (5)

X-Aware (5)

X-Mitigation (5)

5G (4)

AHB (4)

AMS Engines (4)

AMS Simulation (4)

Architectural Verification (4)

Batch and Debug (4)

Bi-Directional (4)

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Bit Width (4)

Boolean (4)

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CDC Violations (4)

CPU Model (4)

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Coverage Achievement (4)

DVFS (4)

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Deprecated (4)

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Determinism (4)

Digital Domain (4)

DisplayPort (4)

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ECO (4)

ED-80 (4)

ENV Package (4)

Enumeration (4)

Equivalence Validation (4)

Equivalent RTL (4)

Fault Coverage (4)

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Fault List (4)

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Formal Closure (4)

Formal Models (4)

HDMI (4)

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ICE Mode (4)

IEEE (4)

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In-Circuit Simulation (4)

In-System Test (4)

Initial States (4)

Instantiate (4)

LFM (4)

Language Constructs (4)

Large Language Models (4)

Mathworks (4)

Mitigation Architecture (4)

Monitor (4)

November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

Packet Transfer (4)

Parallel Compile (4)

Phase Objections (4)

Pipe Interface (4)

Plusargs (4)

Power Constraints (4)

Protocol Checkers (4)

Proxy Class (4)

QEMU (4)

QoR (4)

Questa Design Solutions (4)

RTL Verification (4)

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Race Conditions (4)

Reconfiguration (4)

Resource Utilization (4)

Retargeting Flow (4)

Risk Mitigation (4)

Semantics (4)

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Static Timing (4)

Stream (4)

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Subscriber (4)

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Synergistic Verification (4)

Synthesizable (4)

Tcl/Tk (4)

Test Ranking (4)

Time Cone (4)

Tool Optimization (4)

Toolkit (4)

Top Down (4)

Trust Verification (4)

UCIS (4)

UEC (4)

UPF 3.0 (4)

UPF 4.0 (4)

UVM 1.1d (4)

UVM 1.2 (4)

UVM Monitor (4)

Unidirectional (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

VA Live 2026 - Silicon Valley (4)

VPM (4)

Vectors (4)

Verification Blueprint (4)

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Wave Window (4)

$display (3)

1.2 (3)

AMS Verification (3)

APB3 (3)

Abstract Class (3)

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Airborne Electronic Hardware (3)

Analysis Components (3)

Base Test (3)

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Block Diagram (3)

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CDC Signals (3)

CSI-2 (3)

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Certification (3)

Clock Definitions (3)

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Clocking (3)

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Connect Phase (3)

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JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

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Level-shifter (3)

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MC2 (3)

MUX (3)

Mailboxes (3)

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Memory Debug (3)

Method (3)

NRRs (3)

NoC (3)

OSVVM (3)

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Observer (3)

Open Architecture (3)

Operating State (3)

PCI-SIG (3)

Package Organization (3)

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Phase-Level (3)

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Power Architecture (3)

Power Consumption (3)

Power Gating (3)

Protocol Layers (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

Radiation Mitigation (3)

Re-targeting (3)

Real Number Modeling (3)

Regime (3)

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Routines (3)

SDC (3)

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Scripting (3)

Security Coverage (3)

Security Vulnerabilities (3)

Semaphores (3)

Sign-Off Methodology (3)

Signal Property (3)

Signal-Level (3)

Single Step Debug (3)

Singleton (3)

Slave Agent (3)

Soft Reset (3)

Source Code Management (3)

Specification Driven Formal (3)

Spiral Refinement (3)

State Transition (3)

Static Lists (3)

Static Properties (3)

Subsystem (3)

System Confidence (3)

System Verification (3)

TBX (3)

TDISP (3)

Task Call (3)

Test Realization (3)

Timing Analysis (3)

Timing Integrity (3)

Transaction Layer (3)

Transitive (3)

Type Casting (3)

Typedef (3)

UEFI (3)

Unreachable Code (3)

Utilization (3)

iTBA (3)

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October 2015

Getting ISO 26262 Faults Straight
Functional Safety Oct 23, 2015 Avidan Efody Article

September 2015

New Low Power Verification Techniques
Low Power Sep 23, 2015 Ellie Burns Webinar
Beyond UVM Registers: Better, Faster, Smarter
UVM - Universal Verification Methodology Sep 10, 2015 Rich Edelman Paper
Beyond UVM Registers: Better, Faster, Smarter
UVM - Universal Verification Methodology Sep 10, 2015 Rich Edelman pdf
New School Thinking for Fast and Efficient Verification Using EZ-VIP
Verification IP Sep 02, 2015 Jason Polychronopoulos Webinar
New School Regression Control
Verification Management Sep 01, 2015 Darron May Webinar

August 2015

Evolution of Debug
Debug Aug 25, 2015 Gordon Allan Webinar
Conclusion: Impact of Design Size on First Silicon Success
Planning, Measurement and Analysis Aug 22, 2015 Harry Foster link
Part 12: IC/ASIC Verification Results Trends
Planning, Measurement and Analysis Aug 17, 2015 Harry Foster link
Part 11: IC/ASIC Power Management Trends
Planning, Measurement and Analysis Aug 10, 2015 Harry Foster link

July 2015

Evolution of Debug
Debug Jul 28, 2015 Gordon Allan pdf
Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Jul 27, 2015 Harry Foster link
Part 9: IC/ASIC Verification Technology Adoption Trends
Planning, Measurement and Analysis Jul 19, 2015 Harry Foster link
Unleashing the Full Power of UPF Power States
Low Power Jul 17, 2015 pdf
Part 8: IC/ASIC Resource Trends
Planning, Measurement and Analysis Jul 13, 2015 Harry Foster link
Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Jul 08, 2015 Harry Foster link
EZ Verification with Questa Verification IP
Verification IP Jul 06, 2015 Jason Polychronopoulos pdf
New School Connectivity Checking
Formal Verification Jul 01, 2015 Mark Eslinger Webinar

June 2015

Power Aware CDC Verification
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Track
Power Aware CDC Introduction and Overview
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Understanding Low Power Impact on CDC Logic
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Describing Low Power Logic with UPF
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Integrating Power Aware CDC into a Design Flow
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Questa CDC Demo: Power Aware
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Verification Methodology Cookbooks
Standards Jun 29, 2015 Verification Methodology Team Cookbook