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April 2013

Getting Started with UPF
Low Power Apr 08, 2013 Erich Marschner Session
Introduction to Power Aware Verification
Low Power Apr 08, 2013 Erich Marschner Session
Overview of UPF
Low Power Apr 08, 2013 Erich Marschner Session
Power Aware Verification
Low Power Apr 05, 2013 Erich Marschner Track
Functional Verification Study - 2012
Planning, Measurement and Analysis Apr 01, 2013 Harry Foster Session

March 2013

UVM 1.1d Class Reference
UVM - Universal Verification Methodology Mar 07, 2013 html

February 2013

Bringing Verification and Validation under One Umbrella
Acceleration Feb 22, 2013 Hans Van Der Schoot Article
System Level Code Coverage using Vista Architect and SystemC
Coverage Feb 22, 2013 Ken P. Mccarty - Siemens Eda Article
The Evolution of UPF: What’s Next?
Low Power Feb 22, 2013 Erich Marschner Article
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
SystemVerilog Feb 22, 2013 Ajeetha Kumari, Srinivasan Venkataramanan - Cvc Pvt. Ltd. Article
SVA in a UVM Class-based Environment
SystemVerilog Feb 22, 2013 Ben Cohen Article
The Formal Verification of Design Constraints
Formal Verification Feb 22, 2013 Ajay Daga - Fishtail Design Automation Article
OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale”
UVM - Universal Verification Methodology Feb 22, 2013 Mark Litterick, Verilab Gmbh Article
Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
UVM - Universal Verification Methodology Feb 07, 2013 Rich Edelman pdf
Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
UVM - Universal Verification Methodology Feb 07, 2013 Rich Edelman Paper

January 2013

Improve AMS Verification Quality
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Extend Structured Formal Verification to AMS
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Extend Power-Aware Verification to AMS
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Analog Aspects in AMS
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Overview to Improve AMS Quality
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
AMS Design Configuration Schemes
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Mixing Languages
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Design Topologies
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Design Methodologies
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session
Analog/Mixed-Signal Domain
Analog Mixed-Signal Jan 25, 2013 Ahmed Eisawy Session

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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