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SIEMENS Verification Academy

Browse all content in Siemens Verification Academy with the tag hybrid virtual platform

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March 2014

  • Sequence-Driver Use Models

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Driver Sequence API

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Bidirectional Protocols

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Analysis

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Analysis Port

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Analysis Connections

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Configuring Registers

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Built-in Register Sequences

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Metric Analyzers

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Objections

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Separate Top-Level Modules

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Split Transactors

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Back Pointers

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Defining an API

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Emulation-Ready Testbench Examples

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Sequence Priority

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Overriding Sequences and Sequence Items

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Layering Sequences

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Locking or Grabbing a Sequencer

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Hierarchical Sequences

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Register-Level Stimulus

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Register Model & Structure

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Register Sequence Examples

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Generating Register Models

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

  • Integrating a UVM Register Model in a Testbench - Implementation

    UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter