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Metric Validation (6)

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December 2019 - Volume 15 Issue 3 (5)

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November 2018 - Volume 14 Issue 3 (4)

PCIe Gen 6 (4)

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July 2023 - Volume 19 Issue 2 (3)

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UVM 1.1d (3)

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Shift Left (2)

Sideband Packet (2)

Sign-Off Methodology (2)

Signal Wait (2)

Signal-Level (2)

Silicon Lifecycle Management (2)

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November 2015

UVM Forum Seminar - 2015: UVM Everywhere: Industry Drivers, Best Practices, and Solutions
Standards Nov 24, 2015 pdf
ISO 26262 Fault Analysis – Worst Case is Really the Worst
Functional Safety Nov 10, 2015 Avidan Efody Article
Memories Are Made Like This
Verification IP Nov 01, 2015 Mark Peryer Article
A New Stimulus Model for CPU Instruction Sets
Coverage Nov 01, 2015 Staffan Berg, Mike Andrews - Siemens Eda Article
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
Debug Nov 01, 2015 Eric Rentschler - Siemens Eda Article
Hardware Emulation: Three Decades of Evolution - Part III
Acceleration Nov 01, 2015 Dr. Lauro Rizzatti - Rizzatti Llc Article
QVIP Provides Thoroughness in Verification
Verification IP Nov 01, 2015 Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd. Article
Minimizing Constraints to Debug Vacuous Proofs
Formal Verification Nov 01, 2015 Anshul Jain - Oski Technology Article
A Generic UVM Scoreboard
UVM - Universal Verification Methodology Nov 01, 2015 Jacob Andersen, Kevin Seffensen, Peter Jensen - Syosil Aps Article

October 2015

Getting ISO 26262 Faults Straight
Functional Safety Oct 26, 2015 Avidan Efody link
Getting ISO 26262 Faults Straight
Functional Safety Oct 23, 2015 Avidan Efody Article

September 2015

Low Power Verification Techniques
Low Power Sep 23, 2015 Ellie Burns Webinar
Beyond UVM Registers: Better, Faster, Smarter
UVM - Universal Verification Methodology Sep 10, 2015 Rich Edelman Paper
Beyond UVM Registers: Better, Faster, Smarter
UVM - Universal Verification Methodology Sep 10, 2015 Rich Edelman pdf
New School Thinking for Fast and Efficient Verification Using EZ-VIP
Verification IP Sep 02, 2015 Jason Polychronopoulos Webinar
New School Regression Control
Verification Management Sep 01, 2015 Darron May Webinar

August 2015

Evolution of Debug
Debug Aug 25, 2015 Gordon Allan Webinar

July 2015

Evolution of Debug
Debug Jul 28, 2015 Gordon Allan pdf
Unleashing the Full Power of UPF Power States
Low Power Jul 17, 2015 pdf
EZ Verification with Questa Verification IP
Verification IP Jul 06, 2015 Jason Polychronopoulos pdf
New School Connectivity Checking
Formal Verification Jul 01, 2015 Mark Eslinger Webinar

June 2015

Power Aware CDC Verification
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Track
Power Aware CDC Introduction and Overview
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Understanding Low Power Impact on CDC Logic
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Describing Low Power Logic with UPF
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

CDC Webinar

Wednesday, Jan 21st-8:00 AM PST

Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection

AI/ML Webinar

Wednesday, Jan 28th-8:00 AM PST

Supercharge your CDC & RDC Analysis with The Power of AI/ML

User2User Speaker Program

Become a Speaker at User2User 2026 | Santa Clara, CA | Munich, Germany

VA Live Silicon Valley

Wednesday, Feb 04th-9:30 AM PST

Avery Verification IP for AI/ML/HPC | Santa Clara, CA

Low Power Webinar

Wednesday, Feb 11th-12:00 PM PST

Don’t Miss CDC Bugs in Low Power Designs!: Formal Meets Power Aware CDC

PCIe® Gen7 Webinar

Wednesday, Feb 18th-10:00 AM PST

Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification

FPU Verification Webinar

Wednesday, Feb 25th-8:00 AM PST

AI Assisted FPU Verification Using Questa One SFV

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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