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April 2016

Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
Low Power Apr 13, 2016 Joe Hupcey pdf

March 2016

Questa Visualizer - Power Aware Debug
Debug Mar 18, 2016 Chuck Seeley Demo
Introducing the Verification Academy Patterns Library!
Planning, Measurement and Analysis Mar 16, 2016 Harry Foster link
Walking
Planning, Measurement and Analysis Mar 16, 2016 Harry Foster pdf
Strategy
Planning, Measurement and Analysis Mar 16, 2016 Harry Foster pdf
Certus™ Silicon Debug: Don’t Prototype Without It
Simulation Mar 07, 2016 Verification Horizons Article
Reusable Verification Framework
Simulation Mar 03, 2016 Verification Horizons Article
Simplified UVM for FPGA Reliability: UVM for “Sufficient Elemental Analysis” in DO-254 Flows
Functional Safety Mar 02, 2016 Verification Horizons Article
A Good Plan, Plus Automation, Plus the Right Tools, Equals...Useful.
Standards Mar 02, 2016 Tom Fitzpatrick Article
DO-254 Compliant UVM VIP Development
Functional Safety Mar 02, 2016 Verification Horizons Article
Simplifying Generation of DO-254 Compliant Verification Documents for AEH Devices
Functional Safety Mar 02, 2016 Verification Horizons Article
Complex Signal Processing Verification under DO-254 Constraints
Functional Safety Mar 02, 2016 Verification Horizons Article
Nine Effective Features of NVMe® Questa® Verification IP to Help You Verify PCIe® Based SSD Storage
Simulation Mar 02, 2016 Verification Horizons Article
Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Verification IP Mar 02, 2016 Saumya Agrawal Article
Total Recall: What to Look for in a Memory Model Library
Simulation Mar 02, 2016 Mark Peryer Article
MIPI C-PHY™: Man of the Hour
Simulation Mar 02, 2016 Verification Horizons Article
The Verification Academy Patterns Library
Planning, Measurement and Analysis Mar 02, 2016 Harry Foster Article
First Time Unit Testing Experience Report with SVUnit
Planning, Measurement and Analysis Mar 02, 2016 Neil Johnson Article
An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
Standards Mar 02, 2016 Verification Horizons Article
QVM: Enabling Organized, Predictable, and Faster Verification Closure
Planning, Measurement and Analysis Mar 02, 2016 Verification Horizons Article
Increased Efficiency with Questa VRM and Jenkins Continuous Integration
Verification Management Mar 01, 2016 Thomas Ellis Article

February 2016

Software-Driven Testing of AXI Bus in a Dual Core ARM® System
Standards Feb 29, 2016 Mark Olen Article
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2016 Avidan Efody Paper
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2016 Avidan Efody pdf
The Downside of Advanced Verification
SystemVerilog Feb 22, 2016 Neil Johnson Session

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Formal Security Webinar

Explore How to Protect Against Data Corruption with Formal Security Verification

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

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