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September 2021 - Volume 17 Issue 2 (12)

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October 2017

Editor Insight
Formal Verification Oct 10, 2017 Harry Foster Session
Easy Solutions
Formal Verification Oct 10, 2017 Jin Hou Session
Assertion Complexity Reduction
Formal Verification Oct 10, 2017 Jin Hou Session
Design Complexity Reduction
Formal Verification Oct 10, 2017 Jin Hou Session
Advanced Topics
Formal Verification Oct 10, 2017 Jin Hou Session

September 2017

DAC 2013 Academy PDF Presentation: New Features in IEEE 1801-2013 - Mentor Graphics
Standards Sep 12, 2017 pdf
DAC 2013 Academy PDF Presentation: Intelligent Testbench Automation - Don't be Constrained - Mentor Graphics
Standards Sep 12, 2017 pdf
DAC 2012 Academy PDF Presentation: Verification of Low Power SoCs with IEEE UPF
Standards Sep 12, 2017 pdf
Basic UVM Code Examples
Standards Sep 12, 2017 zip
DAC 2012 Academy PDF Presentation: Bringing UVM to Life
Standards Sep 12, 2017 pdf
DAC 2013 Academy PDF Presentation: The New SystemVerilog 2012 Standard - Sunburst Design
Standards Sep 12, 2017 pdf
DAC 2013 Academy PDF Presentation: Power Aware Verification Getting Started with UPF - Mentor Graphics
Standards Sep 12, 2017 pdf
Productivity and Coverage in UVM Seminar - All Slides Zip
Standards Sep 12, 2017 zip
Guidelines for Crafting XLerated SystemVerilog OVCs
SystemVerilog Sep 12, 2017 pdf
DAC 2012 Academy PDF Presentation: Resistance is Futile - Learning to love UVM!
Standards Sep 12, 2017 pdf
DAC 2013 Academy PDF Presentation: UPF-Based Verification for Cypress PSOC - Cypress
Standards Sep 12, 2017 pdf
DAC 2013 Academy PDF Presentation: UVM - Out of Committee into Productivity - Mentor Graphics
Standards Sep 12, 2017 pdf
DAC 2012 Academy PDF Presentation: SystemVerilog Tricks for Design & Verification
Standards Sep 12, 2017 pdf
How Microsemi Uses Questa Formal Connectivity Check to Improve Quality and Productivity
Formal Verification Sep 08, 2017 Mitchell Poplingher Article
Coverage & Plan-Driven Verification for FPGAs
FPGA Verification Sep 06, 2017 Brian Mathewson Webinar
Questa Clock-Domain Crossing
Clock-Domain Crossing Sep 05, 2017 Doug Smith Demo
Visualizer: Livesim / Interactive
Debug Sep 05, 2017 Tom Kiley Track
Automatic X Tracing in Your Design
Debug Sep 05, 2017 Tom Kiley Demo
Wave Windows Features
Debug Sep 05, 2017 Tom Kiley Demo
FSM Viewer
Debug Sep 05, 2017 Tom Kiley Demo

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Debug Webinar

Wednesday, Mar 05th-8:00 AM PST

Faster Debug of Complex Testbenches Using Visualizer

FPU Webinar

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

ISO 26262 Webinar

Wednesday, Mar 12th-8:00 AM PDT

Safety Analysis for Automotive Chips Based on ISO 26262

Browse all content in Siemens Verification Academy with the tag control logic

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October 2017

September 2017