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June 2017 - Volume 13 Issue 2 (2)

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August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Machine Learning Aug 31, 2019 Brucek Khailany link
Assuring the Integrity of RISC-V Cores and SoCs
Formal Verification Aug 21, 2019 Nicolae Tusinschi pdf
A New Approach to Low Power Verification - Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava pdf
A New Approach to Low-Power Verification: Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava Paper
Coverage Driven Verification of NVMe Using Questa VIP
Verification IP Aug 21, 2019 pdf
Using HLS to Accelerate Computer Vision for Autonomous Drive
High-Level Synthesis Aug 20, 2019 pdf
Source Code Download: Fun with UVM Sequences - Coding and Debugging
Standards Aug 20, 2019 tar
Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models
Coverage Aug 02, 2019 Thomas Ellis pdf
Technical Paper: Moving Beyond Assertions - An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
Standards Aug 02, 2019 pdf
Technical Paper: UVM IEEE Shiny Object
Standards Aug 02, 2019 pdf
Technical Paper: Results Checking Strategies with Portable Stimulus
Standards Aug 02, 2019 pdf
Technical Paper: Transaction Recording Anywhere Anytime
Standards Aug 02, 2019 pdf
Improving Verification Predictability and Efficiency Using Big Data
Planning, Measurement and Analysis Aug 02, 2019 Darron May pdf

July 2019

Visualizer™ Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!
Simulation Jul 17, 2019 Rich Edelman Article
Is It Magic, or Ingenious People Working with Remarkably Advanced Technology?
Simulation Jul 16, 2019 Verification Horizons Article
An Emulation Strategy for AI and ML Designs
Machine Learning Jul 15, 2019 Vijay Chobisa pdf
Deep Learning Accelerator Using HLS
High-Level Synthesis Jul 15, 2019 pdf
DAC 2019 Academy PDF Presentation: Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer
Standards Jul 15, 2019 pdf
DAC 2019 Academy PDF Presentation: What's Missing and What Should Be Next for SystemVerilog
Standards Jul 15, 2019 pdf
Streamlining Plan & Requirements Driven Verification
Planning, Measurement and Analysis Jul 12, 2019 pdf
Improving Verification Throughput of Today’s Complex Mixed-Signal ICs
Analog Mixed-Signal Jul 12, 2019 pdf
Selecting the Most Productive SoC Design Verification Techniques
Planning, Measurement and Analysis Jul 12, 2019 pdf
Veloce HYCON - OS-aware IP Development Solution
Acceleration Jul 12, 2019 pdf
RISC-V Core and SoC: Compliance, Verification, Customization
Verification IP Jul 11, 2019 Larry Lapides pdf
Emulation to Prototype - What’s Eating Your Productivity?
Acceleration Jul 11, 2019 pdf

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag uvmf

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August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning

Assuring the Integrity of RISC-V Cores and SoCs

A New Approach to Low Power Verification - Power Aware Apps

A New Approach to Low-Power Verification: Power Aware Apps

Coverage Driven Verification of NVMe Using Questa VIP

Using HLS to Accelerate Computer Vision for Autonomous Drive

Source Code Download: Fun with UVM Sequences - Coding and Debugging

Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models

Technical Paper: Moving Beyond Assertions - An Innovative Approach to Low-Power Checking Using UPF Tcl Apps

Technical Paper: UVM IEEE Shiny Object

Technical Paper: Results Checking Strategies with Portable Stimulus

Technical Paper: Transaction Recording Anywhere Anytime

Improving Verification Predictability and Efficiency Using Big Data

July 2019

Visualizer™ Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!

Is It Magic, or Ingenious People Working with Remarkably Advanced Technology?

An Emulation Strategy for AI and ML Designs

Deep Learning Accelerator Using HLS

DAC 2019 Academy PDF Presentation: Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer

DAC 2019 Academy PDF Presentation: What's Missing and What Should Be Next for SystemVerilog

Streamlining Plan & Requirements Driven Verification

Improving Verification Throughput of Today’s Complex Mixed-Signal ICs

Selecting the Most Productive SoC Design Verification Techniques

Veloce HYCON - OS-aware IP Development Solution

RISC-V Core and SoC: Compliance, Verification, Customization

Emulation to Prototype - What’s Eating Your Productivity?