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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

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December 2019 - Volume 15 Issue 3 (5)

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March 2018 - Volume 14 Issue 1 (5)

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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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June 2013 - Volume 9 Issue 2 (3)

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June 2017 - Volume 13 Issue 2 (2)

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March 2017 - Volume 13 Issue 1 (2)

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December 2017 - Volume 13 Issue 3 (1)

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June 2012 - Volume 8 Issue 2 (1)

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March 2016 - Volume 12 Issue 1 (1)

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September 2021

Questa AutoCheck - Advanced Linting
Questa Design Solutions Sep 14, 2021 Mark Eslinger Demo
Questa X-Check: Identify "X" Issues
Formal Verification Sep 14, 2021 Mark Eslinger Demo
Questa Lint - Find and Fix RTL Issues
Questa Design Solutions Sep 14, 2021 Tom Carlstedt-Duke Demo
Questa CDC Verification
Questa Design Solutions Sep 14, 2021 Kurt Takara Demo
Python and the UVM
Python Sep 09, 2021 Ray Salemi link
Questa Reset Domain Crossing (RDC)
Reset-Domain Crossing Sep 02, 2021 Atul Sharma Demo
What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Tom Fitzpatrick Article
Digital Thread, Digital Twin, and IC Development
Functional Safety Sep 01, 2021 Ray Salemi Article
Addressing the Trends and Challenges of Automotive IC Development
Functional Safety Sep 01, 2021 Ann Keffer Article
Deploying HLS in a DO-254/ED-80 Workflow
Functional Safety Sep 01, 2021 Tammy Reeve - Patmos Engineering Services Article
Hardware-Assisted Verification Through the Years
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Acceleration Sep 01, 2021 Stephen Bailey Article
"Hug the Debug" – Before It’s Too Late
Debug Sep 01, 2021 Sumit Vishwakarma Article
Questa Visualizer Adds Coverage Analysis to the Platform
Debug Sep 01, 2021 Yara Esam - Siemens Eda Article
Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article
Expediting Simulation Turn-around Time with Incremental Build Flow
Simulation Sep 01, 2021 Neil Johnson Article
Standards Participation at Siemens EDA
Standards Sep 01, 2021 Dave Rich Article

August 2021

IP Security: Keys to Early Identification of Security Vulnerabilities
Formal Verification Aug 27, 2021 John Hallman Webinar
UVM Connect 2.3 Primer
UVMC Aug 25, 2021 John Stickley pdf
RDC Overview & Questa RDC Methodology
Reset-Domain Crossing Aug 21, 2021 Atul Sharma Webinar
RDC Overview & Questa RDC Methodology
Questa Design Solutions Aug 21, 2021 Atul Sharma pdf
Should I Kill My Formal Run? Part 1: Formal Run is In-Progress
Formal Verification Aug 20, 2021 Dr. Jeremy Levitt Webinar
Exploration into Safety Analysis Techniques That Optimize the Safety Workflow
Functional Safety Aug 13, 2021 Ann Keffer Webinar
UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
UVM Framework Aug 05, 2021 Pedram Riahi - Raytheon Webinar

New Master’s-level Course

Functional Verification of Digital Logic

Debug Webinar

Wednesday, Mar 05th-8:00 AM PST

Faster Debug of Complex Testbenches Using Visualizer

ISO 26262 Webinar

Wednesday, Mar 12th-8:00 AM PDT

Safety Analysis for Automotive Chips Based on ISO 26262

IC/ASIC & FPGA Trends

2024 Siemens EDA and Wilson Research Group Functional Verification Study

Safety & Security Webinar

FPGA Equivalence Checking from RTL to the Bitstream

Browse all content in Siemens Verification Academy with the tag Acceleration

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September 2021

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