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September 2021 - Volume 17 Issue 2 (12)

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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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June 2017 - Volume 13 Issue 2 (2)

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Questa Reset Domain Crossing (RDC)
Reset-Domain Crossing Sep 02, 2021 Atul Sharma Demo
What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Tom Fitzpatrick Article
Digital Thread, Digital Twin, and IC Development
Functional Safety Sep 01, 2021 Ray Salemi Article
Addressing the Trends and Challenges of Automotive IC Development
Functional Safety Sep 01, 2021 Ann Keffer Article
Deploying HLS in a DO-254/ED-80 Workflow
Functional Safety Sep 01, 2021 Tammy Reeve - Patmos Engineering Services Article
Hardware-Assisted Verification Through the Years
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Acceleration Sep 01, 2021 Stephen Bailey Article
"Hug the Debug" – Before It’s Too Late
Debug Sep 01, 2021 Sumit Vishwakarma Article
Questa Visualizer Adds Coverage Analysis to the Platform
Debug Sep 01, 2021 Yara Esam - Siemens Eda Article
Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article
Expediting Simulation Turn-around Time with Incremental Build Flow
Simulation Sep 01, 2021 Neil Johnson Article
Standards Participation at Siemens EDA
Standards Sep 01, 2021 Dave Rich Article

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag uvmf

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October 2021

CDC Philosophy: The existential questions of constraints, waivers, and truth

TLM 1.0 in pyuvm

September 2021

Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy

Exhaustive Scoreboarding and Data Integrity Verification Made Easy

Improving Initial RTL Quality

Improving Initial RTL Quality | Japanese

Improving Initial RTL Quality

Questa AutoCheck - Advanced Linting

Questa X-Check: Identify "X" Issues

Questa Lint - Find and Fix RTL Issues

Questa CDC Verification

Python and the UVM

Questa Reset Domain Crossing (RDC)

What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You

Digital Thread, Digital Twin, and IC Development

Addressing the Trends and Challenges of Automotive IC Development

Deploying HLS in a DO-254/ED-80 Workflow

Hardware-Assisted Verification Through the Years

Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive

Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs

"Hug the Debug" – Before It’s Too Late

Questa Visualizer Adds Coverage Analysis to the Platform

Verifying a DDR5 Memory Subsystem

Expediting Simulation Turn-around Time with Incremental Build Flow

Standards Participation at Siemens EDA