A Novel Approach for HW/SW Co-verification Leveraging PSS to Orchestrate UVM and C Tests
In this paper, a complete framework will be introduced to ease HW/SW co-verification. Two use models will be demonstrated to go through the proposed methodology, which will help verification engineers and teams to improve SoC verification, by writing one PSS model which can execute C tests as well as UVM sequences to cover the different aspects of HW/SW co-verification.
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