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The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
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Accelerating Functional Coverage with Questa One CX

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Tackling Emerging DFT Verification Challenges with Questa One

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Faster Debug of Complex Testbenches using Visualizer

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Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

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Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Functional Verification Workflow for Trusted and Assured Microelectronics

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Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

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Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

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Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

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Introduction to SystemVerilog Assertions

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

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Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

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Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

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Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

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Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

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January 2019

Deploying A Metrics Driven Low Power Methodology for Your RTL IP
Low Power Jan 28, 2019 Qazi Ahmed Webinar
Low Power Verification & Analysis with Emulation
Low Power Jan 28, 2019 Shantanu Samant Webinar
Productive Low Power Debug Across All Engines and Flows
Debug Jan 28, 2019 Gordon Allan Webinar

December 2018

How to Unearth Deep Bugs Using Formal Bug Hunting Techniques
Formal Verification Dec 23, 2018 Mark Eslinger Webinar

September 2018

UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick Webinar

August 2018

Using Automation to Close the Loop Between Functional Requirements and their Verification
Planning, Measurement and Analysis Aug 10, 2018 Brian Craw Webinar

March 2018

How Formal Reduces Fault Analysis for ISO 26262
Functional Safety Mar 27, 2018 Doug Smith Webinar
Requirement Tracing in the ISO 26262 World
Functional Safety Mar 27, 2018 Charles Battikha Webinar
From Analysis to Fault Campaigns - ISO 26262
Functional Safety Mar 27, 2018 Charles Battikha Webinar
Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs
Low Power Mar 07, 2018 Ellie Burns Webinar

December 2017

Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?
Debug Dec 12, 2017 Neil Bulman Webinar

November 2017

An Introduction to DO-254 and Advanced Verification
Functional Safety Nov 02, 2017 Tom Fitzpatrick Webinar

September 2017

Coverage & Plan-Driven Verification for FPGAs
FPGA Verification Sep 06, 2017 Brian Mathewson Webinar

July 2017

SystemVerilog OOP Basics used in UVM Verification
SystemVerilog Jul 12, 2017 Dave Rich Webinar

June 2017

Enterprise Ethernet PHY Verification
Verification IP Jun 13, 2017 Akshay Sarup Webinar
Need for Speed - PCIe® GEN4 Verification
Verification IP Jun 13, 2017 Akshay Sarup Webinar
Creating a Thorough Verification Environment in Less Than Two Days
Verification IP Jun 13, 2017 Jason Polychronopoulos Webinar
Trends and Requirements in High Speed Interface Verification
Verification IP Jun 13, 2017 Niraj Mathur Webinar
MIPI® CSI-2 TX Verification
Verification IP Jun 13, 2017 Ivan Ristic Webinar
Leveraging the latest DDR & Flash Memory Models
Verification IP Jun 13, 2017 Jason Polychronopoulos Webinar
USB 3.1 Verification Challenges
Verification IP Jun 13, 2017 Dinesh Tyagi Webinar
Conquering the New IP Economy
Planning, Measurement and Analysis Jun 13, 2017 Harry Foster Webinar

May 2017

SoC Verification with the Questa Flow
FPGA Verification May 17, 2017 Gordon Allan Webinar

March 2017

Testbench Automation - Environment
UVM Framework Mar 17, 2017 Bob Oden Webinar
Testbench Automation - Introduction
UVM Framework Mar 17, 2017 Bob Oden Webinar

151–175 of 221

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