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Show Less

May 2022

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
UVM Framework May 10, 2022 Bob Oden Webinar
How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification
Formal Verification May 10, 2022 Joe Hupcey Webinar
Accelerate Development Using Advanced Debugging Approaches
Debug May 10, 2022 Rich Edelman Webinar
Collaborative Verification Management & Coverage Analysis
Verification Management May 10, 2022 Darron May Webinar
Securing the Electronics Development Chain with IC Integrity Solutions
Formal Verification May 10, 2022 John Hallman Webinar
System Level SoC Verification and Validation Using Emulation and Prototype Platforms
Acceleration May 10, 2022 Vijay Chobisa Webinar
Trust but Verify Your IP with Solido Crosscheck
Analog Mixed-Signal May 10, 2022 Felipe Schneider Webinar

March 2022

Formal 101: Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 Joe Hupcey Webinar
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
Questa Design Solutions Mar 10, 2022 Buu Huynh Webinar

February 2022

‘The Dog Ate my RTL’ Doesn’t Work Anymore
Questa Design Solutions Feb 15, 2022 Joe Hupcey Webinar

January 2022

Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee Webinar

September 2021

Improving Initial RTL Quality
Questa Design Solutions Sep 15, 2021 Chris Giles Webinar

August 2021

IP Security: Keys to Early Identification of Security Vulnerabilities
Formal Verification Aug 27, 2021 John Hallman Webinar
Reset-Domain Crossing Overview & Questa RDC Methodology
Reset-Domain Crossing Aug 21, 2021 Atul Sharma Webinar
Should I Kill My Formal Run? Part 1: Formal Run is In-Progress
Formal Verification Aug 20, 2021 Dr. Jeremy Levitt Webinar
Exploration into Safety Analysis Techniques that Optimize the Safety Workflow
Functional Safety Aug 13, 2021 Ann Keffer Webinar

July 2021

Managing Requirements in a Functional Safety Environment
Functional Safety Jul 29, 2021 Thorsten Stahlberg - Siemens Eda Webinar
Using Formal Verification in Daily Work
Formal Verification Jul 29, 2021 Dr. Abdelouahab Ayari - Siemens Eda Webinar
Digital Functional Verification for Safety-Critical Automotive Applications
Functional Safety Jul 29, 2021 Michael Bierl - Siemens Eda Webinar
CDC Verification: Beyond Structural Analysis
Clock-Domain Crossing Jul 29, 2021 Mark Handover Webinar
Mitigating the Effects of Random Hardware Faults
Functional Safety Jul 29, 2021 Dirk Hansen - Siemens Eda Webinar

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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