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The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
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Accelerating Functional Coverage with Questa One CX

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Tackling Emerging DFT Verification Challenges with Questa One

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Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

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Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Functional Verification Workflow for Trusted and Assured Microelectronics

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Securing your FPGA Design from RTL through to the Bitstream

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Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

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Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

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Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

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Introduction to SystemVerilog Assertions

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

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Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

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Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

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Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

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Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

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August 2021

UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level
UVM Framework Aug 05, 2021 Pedram Riahi - Raytheon Webinar

July 2021

Managing Requirements in a Functional Safety Environment
Functional Safety Jul 29, 2021 Thorsten Stahlberg - Siemens Eda Webinar
Using Formal Verification in Daily Work
Formal Verification Jul 29, 2021 Dr. Abdelouahab Ayari - Siemens Eda Webinar
Digital Functional Verification for Safety-Critical Automotive Applications
Functional Safety Jul 29, 2021 Michael Bierl - Siemens Eda Webinar
CDC Verification: Beyond Structural Analysis
Clock-Domain Crossing Jul 29, 2021 Mark Handover Webinar
Mitigating the Effects of Random Hardware Faults
Functional Safety Jul 29, 2021 Dirk Hansen Webinar
AMS Functional Verification for Safety-Critical Automotive Applications
Functional Safety Jul 29, 2021 Sumit Vishwakarma Webinar
A Path to Develop Safe ICs - Part 2
Functional Safety Jul 29, 2021 Stephanie Dournelle, Paul Williams - Siemens Eda Webinar
A Path to Develop Safe ICs - Part 1
Functional Safety Jul 29, 2021 Stephanie Dournelle - Siemens Eda Webinar
Extending the Role of Test and In-System Test to Meet Automotive Safety and Security Requirements
Functional Safety Jul 29, 2021 Lee Harrison Webinar
Hardware-Accelerated & Software-Driven Verification
Acceleration Jul 29, 2021 Ajay Sharma Webinar
Automotive SOTIF Compliance for Arm with PAVE360
Functional Safety Jul 29, 2021 Antonio Priore - Arm, Joe Dailey - Siemens, Tapan Vikas - Siemens Eda Webinar
Are Random Hardware Faults Common?
Functional Safety Jul 29, 2021 Dirk Hansen Webinar
Traceability for Automotive Standards Compliance
Functional Safety Jul 29, 2021 Darron May Webinar
Part II: Verification of PCIe® IP
Verification IP Jul 15, 2021 Stephane Hauradou Webinar

June 2021

Leveraging Advancements in UPF 3.1 for Effective Design and Verification
Low Power Jun 23, 2021 Gabriel Chidolue Webinar
Part I: Introduction to PCIe® Gen 6
Verification IP Jun 08, 2021 Stephane Hauradou Webinar

May 2021

Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Functional Safety May 04, 2021 Jacob Wiltgen Webinar

April 2021

Low Power Considerations for Verification
Low Power Apr 29, 2021 Rick Koster Webinar
A Methodology for Comprehensive CDC+RDC Analysis
Reset-Domain Crossing Apr 20, 2021 Kurt Takara Webinar
Easy Test Writing with a Proxy-driven Testbench
SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar
Making Your DPI-C Interface a Fast River of Data
SystemVerilog Mar 31, 2021 Rich Edelman Webinar
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Low Power Mar 31, 2021 Progyna Khondkar Webinar
Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar

76–100 of 221

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