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December 2016

JUnit Plugin (required)
Planning, Measurement and Analysis Dec 23, 2016 link
Questa VRM
Planning, Measurement and Analysis Dec 23, 2016 Darron May link
Jenkins Release
Planning, Measurement and Analysis Dec 23, 2016 link
Dashboard View (optional)
Planning, Measurement and Analysis Dec 23, 2016 link
Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers
Verification IP Dec 19, 2016 Saurabh Sharma pdf
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal pdf
The Fundamental Power States for UPF Modeling and Power Aware Verification
Low Power Dec 14, 2016 Progyna Khondkar pdf
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara pdf

August 2016

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara pdf
Extending a Traditional VIP to Solve PHY Verification Challenges
Verification IP Aug 26, 2016 pdf
Beyond UVM Registers - Better, Faster, Smarter
UVM - Universal Verification Methodology Aug 25, 2016 Rich Edelman pdf
Total Recall - What to Look for in a Memory Model Library
Verification IP Aug 24, 2016 pdf
SystemVerilog Code Examples
SystemVerilog Aug 24, 2016 Ray Salemi zip
Article: How to instrument your design with simple SystemVerilog assertions
Standards Aug 24, 2016 link
SystemVerilog & UVM Coding & Performance Guidelines
SystemVerilog Aug 24, 2016 pdf
Technical Paper: A Scalable Approach for TLM Across SystemC and SystemVerilog
Standards Aug 24, 2016 pdf
Technical Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog
Standards Aug 24, 2016 pdf
SystemVerilog Performance Guide
SystemVerilog Aug 24, 2016 pdf
SystemVerilog Assertions Design Tricks & SVA Bind Files (slide set 4)
Standards Aug 24, 2016 pdf
SystemVerilog Coding Guide
SystemVerilog Aug 24, 2016 pdf
Technical Paper: Binding SystemVerilog to VHDL Components Using Questa
Standards Aug 24, 2016 pdf
Technical Paper: TLM2 in SystemVerilog
Standards Aug 24, 2016 pdf
Technical Paper: Planning SystemVerilog Adoption
Standards Aug 24, 2016 pdf
Technical Paper: Comparison of VHDL, Verilog and SystemVerilog
Standards Aug 24, 2016 pdf
Technical Paper: VPI for SystemVerilog Goes Dynamic
Standards Aug 24, 2016 pdf

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AI is Changing Verification | Interview with Abhi Kolpekwar

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