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Show Less

July 2017

Applying Big Data Analytics to Today’s Functional Verification Challenge
Planning, Measurement and Analysis Jul 20, 2017 Harry Foster pdf
DAC 2017 Academy PDF Presentation: C'mon ... Quit Screwing-Up the UVM $display Command!!
Standards Jul 20, 2017 pdf
Add Unit Testing To Your Verification Tool Belt
Planning, Measurement and Analysis Jul 20, 2017 Neil Johnson pdf
SystemVerilog Object Oriented Programming Basics used in UVM Verification
SystemVerilog Jul 20, 2017 pdf

June 2017

UVM Debug Editor Insight
UVM - Universal Verification Methodology Jun 14, 2017 Harry Foster pdf
UVM Connectivity Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley pdf
UVM Phase Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley pdf
Memory Leak Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley pdf
UVM Configuration Database Debug
UVM - Universal Verification Methodology Jun 14, 2017 Tom Kiley pdf

March 2017

Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar pdf
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Verification Management Mar 13, 2017 Thomas Ellis pdf
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Verification Management Mar 13, 2017 Thomas Ellis pdf

February 2017

How Formal Reduces Fault Analysis for ISO 26262
Functional Safety Feb 15, 2017 Doug Smith pdf

December 2016

Jenkins Tutorial - Setup, Install, Configuration
Planning, Measurement and Analysis Dec 23, 2016 Darron May pdf
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Planning, Measurement and Analysis Dec 23, 2016 link
Questa VRM
Planning, Measurement and Analysis Dec 23, 2016 Darron May link
Jenkins Release
Planning, Measurement and Analysis Dec 23, 2016 link
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Planning, Measurement and Analysis Dec 23, 2016 link
Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers
Verification IP Dec 19, 2016 Saurabh Sharma pdf
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal pdf
The Fundamental Power States for UPF Modeling and Power Aware Verification
Low Power Dec 14, 2016 Progyna Khondkar pdf
What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara pdf

August 2016

Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts
Clock-Domain Crossing Aug 26, 2016 Kurt Takara pdf
Extending a Traditional VIP to Solve PHY Verification Challenges
Verification IP Aug 26, 2016 pdf
Total Recall - What to Look for in a Memory Model Library
Verification IP Aug 24, 2016 pdf

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AI is Changing Verification | Interview with Abhi Kolpekwar

VHDL Webinar

Wednesday, Nov 12th-8:00 AM PST

Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

User2User

Nov. 19th | 0800 - 1630 US/Eastern

Mid-Atlantic 2025 | Johns Hopkins University | Laurel, Maryland

Debug Webinar

Wednesday, Dec 03rd-8:00 AM PST

VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

Verification Academy Live

Scottsdale, AZ | Dec. 3rd - 9:30 - 5:00 US/MST | Top Golf

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