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March 2024 - Volume 20 Issue 1 (1)

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March 2019

Part 12: IC/ASIC Verification Results Trends
Planning, Measurement and Analysis Mar 13, 2019 Harry Foster link
Five Steps to Quality CDC Verification
Clock-Domain Crossing Mar 13, 2019 Ping Yeung pdf
Formal Apps Take the Bias Out of Functional Verification
Formal Verification Mar 13, 2019 Bill Au pdf
Part 11: IC/ASIC Power Management Trends
Planning, Measurement and Analysis Mar 05, 2019 Harry Foster link

February 2019

The Big Brain Theory: Visualizing SoC Design and Verification Data
Verification Management Feb 28, 2019 pdf
Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Questa Design Solutions Feb 28, 2019 Rohit Jain pdf
UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich pdf
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung pdf
Clock-Domain Crossing (CDC) Challenges in Latch Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara pdf
Low Power Apps: Shaping the Future of Low Power Verification
Low Power Feb 28, 2019 pdf
Formal Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2019 Doug Smith pdf
Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Dave Rich pdf
Choosing a Format for the Portable Stimulus Specification
Portable Stimulus Feb 22, 2019 Matthew Ballance pdf
Part 10: IC/ASIC Language and Library Adoption Trends
Planning, Measurement and Analysis Feb 14, 2019 Harry Foster link
Part 9: IC/ASIC Verification Technology Adoption Trends
Planning, Measurement and Analysis Feb 05, 2019 Harry Foster link

January 2019

Part 8: IC/ASIC Resource Trends
Planning, Measurement and Analysis Jan 29, 2019 Harry Foster link
Accelerating Verification through Verification IP, Configurator and UVM Framework
Verification IP Jan 24, 2019 Sharath Kannareddy pdf
Making Verification Fun Again
UVM Framework Jan 24, 2019 Jonathan Craft pdf
Verification Acceleration for FPGA Designs with Matlab
Acceleration Jan 24, 2019 Jerry Grula - Siemens Eda pdf
Welcome & Overview
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf
ASIC & FPGA SoC Functional Verification Trends
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf
Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Jan 22, 2019 Harry Foster link
Part 6: FPGA Verification Language and Library Adoption Trends
Planning, Measurement and Analysis Jan 15, 2019 Harry Foster link
Part 5: FPGA Verification Technology Adoption Trends
Planning, Measurement and Analysis Jan 07, 2019 Harry Foster link

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