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March 2016 - Volume 12 Issue 1 (5)

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March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

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UPF 4.0 (4)

VA Live 2023 - Austin (4)

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December 2017 - Volume 13 Issue 3 (3)

Design Cycle (3)

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July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

Memory Models (3)

Multi-Core Architectures (3)

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October 2012 - Volume 8 Issue 3 (3)

PCIe Gen 7 (3)

Parallel Simulation (3)

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Python (3)

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UALink (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

Unified Coverage Database (3)

VA Live 2019 - Westford (3)

VA Live 2024 - Austin (3)

VA Live 2024 - Fremont (3)

Validation (3)

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2D/3D (2)

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DVCON 2021 (2)

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Data Link (2)

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December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

Design for Safety (2)

Digital Signal Processing (2)

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Elements List (2)

Ethernet (2)

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GLS (2)

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IEEE (2)

IEEE 754 (2)

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ISA (2)

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Instance Mapping (2)

Instantiate (2)

Intelligent Integration (2)

Interconnect Signals (2)

Jittering (2)

June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

LVS (2)

Level-shifter (2)

Lockstep (2)

Loggers (2)

Logic Cone (2)

MIPI (2)

Machine Readable Specification (2)

March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metastable (2)

Metric Validation (2)

Mixed-Signal Design (2)

Modules (2)

Monitor (2)

Multi-Language Environment (2)

Non-Determinism (2)

Object Oriented Programming (2)

October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

Open Architecture (2)

PAM4 (2)

PCI-SIG (2)

PMHF (2)

Parameter (2)

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Parameterized Tests (2)

Partitioning (2)

Pattern Splitting (2)

Point-to-Point Connections (2)

Polymorphism (2)

Post-silicon Debug (2)

Power Profiling (2)

Power Reduction (2)

Precedence (2)

Profiling (2)

Property Analysis (2)

QCX (2)

Questa Design Solutions (2)

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RDC Violations (2)

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Reference Model (2)

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Reset Value (2)

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Runtime (2)

SFV (2)

SLM (2)

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Scoreboard (2)

Security Vulnerabilities (2)

Shift Left (2)

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Spice (2)

Split Transactor (2)

State Preservation (2)

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Strategy (2)

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Supply Chain (2)

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TLM FIFOS (2)

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UPF 2.0 (2)

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USB (2)

UVMC 2.3.0 (2)

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Ultra Accelerator Link (2)

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osmosis 2024 A&D (2)

$display (1)

2.5D (1)

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AHB (1)

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C-PHY (1)

CMA (1)

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CSI (1)

CSI-2 (1)

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Cloud Computing (1)

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Compute Express Link (1)

Config_db (1)

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Controller Area Network (1)

Counterexample (1)

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D-PHY (1)

DVCon Europe (1)

Debug Methodology (1)

Design Complexity (1)

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Design.bin (1)

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DisplayPort (1)

Dual Domains (1)

Dynamic CDC (1)

ED-80 (1)

EMC (1)

Electronic Design Integration (1)

Elliptic Curve (1)

Embedded Analytics (1)

Embedded Software (1)

Emerging Trends (1)

Enterprise Debug and Analysis (1)

Execution Trace (1)

Factory (1)

Fault Coverage (1)

February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

Flash (1)

Flip-Flop (1)

Floating-Point Hardware (1)

Formal Test Planning (1)

Formal Verification Apps (1)

Functional Monitoring (1)

GPU (1)

Generation (1)

Golden Model (1)

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Host Processor (1)

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IDE (1)

IEC 62304 (1)

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IP Quality (1)

In-Circuit Emulation (1)

In-System Test (1)

Instance (1)

Integer (1)

Integration Level (1)

Interrupts (1)

Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

Logic Faults (1)

Low Latency (1)

MCPs (1)

MUX (1)

March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

Mathworks (1)

Measurement (1)

Memory BIST (1)

Memory Debug (1)

Memory Usage (1)

Model-Based Design (1)

Multi-Cycle Paths (1)

NAND (1)

NLP (1)

NRRs (1)

Non-Resettable Registers (1)

Non-Trivial Bug Escapes (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

Objectives (1)

Objects (1)

Observer (1)

PCIe Gen 4 (1)

PHY (1)

Partitioned Compile (1)

Phases (1)

Phrase Configuration (1)

Portability (1)

Power Gating (1)

Pre-Silicon (1)

Productivity Gap (1)

Property Editor (1)

Prototyping (1)

QEMU (1)

QOS Processor (1)

RAM (1)

RDC Methodology (1)

RDMA (1)

RISC-V Verification Interface (1)

RNG (1)

RTL Emulation (1)

RTL-Aware Design (1)

Re-Spins (1)

Receiver (1)

Recording (1)

Recurrent Neural Networks (1)

Release Notes (1)

Repair Architecture (1)

Reporting (1)

Reset Environment (1)

Reset Tree (1)

Respins (1)

Root Complex (1)

Run Monitor (1)

SA-EDI (1)

SATA (1)

SCE-MI (1)

SOTIF (1)

SPDM (1)

SPI (1)

SafeSPI (1)

Safety Monitoring (1)

Scenario Generation (1)

Security Asset (1)

Security Coverage (1)

Security Protocol and Data Model (1)

Sequencer (1)

Sequential Errors (1)

Sequential Optimization (1)

Signal Processing Domain (1)

Single Root-IO Virtualization (1)

Singleton (1)

Softmodel (1)

Software Layers (1)

Spiral Refinement (1)

Static CDC (1)

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Static RDC (1)

Sub-Module (1)

Subscriber (1)

Supply Set (1)

Systemic Faults (1)

TBX (1)

TDISP (1)

TPU (1)

Test Compression (1)

Test Coverage (1)

Tool Confidence Level (1)

Tool Detection (1)

Tool Impact (1)

Trace Depth (1)

Transaction Layer (1)

Transactional Assertions (1)

Transactors (1)

Transmitter IP (1)

Tunneling (1)

UCIS (1)

UEC (1)

UPF 3.1 (1)

USB 3.0 (1)

USB 3.1 (1)

UVM Simulation (1)

UVM-MS (1)

UVMC 2.1.4 (1)

UVMC 2.2 (1)

UVVM (1)

Unary (1)

Unidirectional (1)

Use Models (1)

VA Live 2023 - El Segundo (1)

VC File (1)

VCMs (1)

VIP - 3.1 (1)

Values (1)

VbyOne (1)

Vectors (1)

Verbose (1)

Verbosity (1)

Verification Component (1)

Verification Run Manager (1)

Virtual Equivalence (1)

Virtual Methods (1)

WRG (1)

Wall-Clock Run-Time (1)

X-Optimism (1)

XML (1)

YAML (1)

eFuse (1)

Show Less

September 2024

Transforming AI with HBM: Siemens’ Avery VIP powers Rambus’ Industry-First HBM4 Memory Controller
Verification IP Sep 18, 2024 Vivek Kaliki - Siemens Eda link
Exploring Essential Concepts in Formal Verification
Formal Verification Sep 18, 2024 Nicolae Tusinschi link
MARLUG - 2024
FPGA Verification Sep 18, 2024 Austin Mam Seminar
Assertions and Benefits of Abstractions in Formal Verification
Formal Verification Sep 11, 2024 Nicolae Tusinschi link
Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Formal Verification Sep 11, 2024 Nicolae Tusinschi Webinar
Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs
Formal Verification Sep 11, 2024 Nicolae Tusinschi pdf
Accelerating Verification of Computational Storage Designs Using Avery NVMe Verification IP
Verification IP Sep 09, 2024 Ujjwal Negi Paper
Accelerating Verification of Computational Storage Designs Using Avery NVMe Verification IP
Verification IP Sep 09, 2024 Ujjwal Negi pdf
Understanding Formal Verification
Formal Verification Sep 05, 2024 Nicolae Tusinschi link

August 2024

UVM Connect 2.3.4 Kit
UVMC Aug 29, 2024 John Stickley tar
UVM Connect 2.3.4 Primer
UVMC Aug 29, 2024 John Stickley pdf
UVM Connect 2.3.4 Release Notes
UVMC Aug 29, 2024 John Stickley txt
The Future of Multi-Die System Verification with UCIe
Verification IP Aug 21, 2024 Justin Bunnell pdf
The Future of Multi-Die System Verification with UCIe
Verification IP Aug 21, 2024 Justin Bunnell Webinar

June 2024

Questa CDC-FX: Metastability Effects Delay Modeling
Clock-Domain Crossing Jun 28, 2024 Kurt Takara Paper
Questa CDC-FX: Metastability Effects Delay Modeling
Clock-Domain Crossing Jun 28, 2024 Kurt Takara pdf
Introducing Smart Verification: Unleashing the Potential of AI within Functional Verification
Machine Learning Jun 24, 2024 Tom Fitzpatrick Conference
Accelerated Confidence in Interface Designs Mixing Software Layers, Hardware Protocols, Physical Connections
Verification IP Jun 24, 2024 Gordon Allan Conference
Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove
Portable Stimulus Jun 24, 2024 Tom Fitzpatrick Conference
Challenges of Developing IPs for AI Chips
Verification IP Jun 24, 2024 Tom Fitzpatrick Conference
The New Leader in Verification IP: Questa + Avery Solutions
Verification IP Jun 04, 2024 Rick Schmidt - Siemens Eda pdf

May 2024

Questa RDC Assist: Accelerate Reset Closure with AI/ML
Reset-Domain Crossing May 22, 2024 Farhad Ahmed Webinar
Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning
Reset-Domain Crossing May 22, 2024 Farhad Ahmed pdf
Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification
Questa Design Solutions May 21, 2024 Chris Giles pdf
Functional Monitoring: From Lab to In-Life
Planning, Measurement and Analysis May 21, 2024 Fady Abushahla - Siemens Eda pdf

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