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March 2016 - Volume 12 Issue 1 (5)

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March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

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VA Live 2023 - Austin (4)

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December 2017 - Volume 13 Issue 3 (3)

Design Analysis (3)

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July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

Memory Models (3)

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October 2012 - Volume 8 Issue 3 (3)

Parallel Simulation (3)

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Python (3)

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UPF 4.0 (3)

UVMC 2.3.3 (3)

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VA Live 2019 - Westford (3)

VA Live 2024 - Austin (3)

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Variable (3)

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2.5D (2)

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December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

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IEEE (2)

IEEE 754 (2)

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ISA (2)

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Interconnect Signals (2)

Jittering (2)

June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

Lockstep (2)

Loggers (2)

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MIPI (2)

Machine Readable Specification (2)

March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metastable (2)

Metric Validation (2)

Mixed-Signal Design (2)

Modules (2)

Monitor (2)

NVM Express (2)

Non-Determinism (2)

Object Oriented Programming (2)

October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

Open Architecture (2)

PAM4 (2)

PCI-SIG (2)

PCIe Gen 7 (2)

PMHF (2)

Parameter (2)

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Partitioning (2)

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Point-to-Point Connections (2)

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Power Architecture (2)

Power Profiling (2)

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Questa Design Solutions (2)

RDC Analysis (2)

RDC Violations (2)

Re-targeting (2)

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SFV (2)

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Scoreboard (2)

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Shift Left (2)

Sign-Off Methodology (2)

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Spice (2)

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Static & Formal Adoption (2)

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Supply Chain (2)

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UALink (2)

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USB (2)

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UVMC 2.3.2 (2)

Universal Approximation (2)

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VRM (2)

VbyOne (2)

Verification Cycles (2)

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osmosis 2024 A&D (2)

$display (1)

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February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

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Generation (1)

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Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

Logic Faults (1)

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MCPs (1)

MUX (1)

March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

Mathworks (1)

Memory BIST (1)

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NAND (1)

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Namespaces (1)

Non-Trivial Bug Escapes (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

OSCI (1)

Objectives (1)

Objects (1)

Observer (1)

PCIe Gen 4 (1)

PHY (1)

Partitioned Compile (1)

Phases (1)

Phrase Configuration (1)

Power Gating (1)

Pre-Silicon (1)

Productivity Gap (1)

Property Analysis (1)

Property Editor (1)

Prototyping (1)

QOS Processor (1)

RAM (1)

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RDMA (1)

RISC-V Verification Interface (1)

RNG (1)

RTL Emulation (1)

RTL-Aware Design (1)

Re-Spins (1)

Receiver (1)

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Reset Tree (1)

Respins (1)

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SATA (1)

SCE-MI (1)

SOTIF (1)

SPDM (1)

SPI (1)

SSD (1)

SafeSPI (1)

Safety Monitoring (1)

Scenario Generation (1)

Security Protocol and Data Model (1)

Sequencer (1)

Sequential Optimization (1)

Signal Processing Domain (1)

Single Root-IO Virtualization (1)

Singleton (1)

Softmodel (1)

Software Layers (1)

Specification Driven Formal (1)

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Static CDC (1)

Strategy (1)

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Subscriber (1)

Supply Set (1)

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TBX (1)

TPU (1)

Tcl/Tk (1)

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Transactors (1)

Transmitter IP (1)

Tunneling (1)

UCIS (1)

UEC (1)

UPF 3.1 (1)

USB 3.0 (1)

USB 3.1 (1)

UVM Simulation (1)

UVM-MS (1)

UVMC 2.1.4 (1)

UVMC 2.2 (1)

UVVM (1)

Ultra Accelerator Link (1)

Unary (1)

Unidirectional (1)

Use Models (1)

VA Live 2023 - El Segundo (1)

VC File (1)

VCMs (1)

VIP - 3.1 (1)

Values (1)

Verbose (1)

Verbosity (1)

Verification Architecture (1)

Verification Component (1)

Verification Run Manager (1)

Virtual Equivalence (1)

Virtual Methods (1)

WRG (1)

Wall-Clock Run-Time (1)

X-Optimism (1)

XML (1)

YAML (1)

eFuse (1)

Show Less

March 2016

Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Mar 12, 2016 Saumya Agrawal - Siemens Eda Paper
Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Verification IP Mar 02, 2016 Saumya Agrawal - Siemens Eda Article
Nine Effective Features of NVMe® Questa Verification IP to Help You Verify PCIe® Based SSD Storage
Verification IP Mar 02, 2016 Saurabh Sharma - Siemens Eda Article
MIPI C-PHY™: Man of the Hour
Verification IP Mar 02, 2016 Yogesh Chaudhary - Siemens Eda Article
Certus™ Silicon Debug: Don’t Prototype Without It
Debug Mar 02, 2016 Doug Amos - Siemens Eda Article
DO-254 Compliant UVM VIP Development
Functional Safety Mar 02, 2016 Ates Berna - Electra Ic Article

February 2016

Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2016 Avidan Efody Paper
Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Functional Safety Feb 28, 2016 Avidan Efody pdf

November 2015

Leveraging Verification IP (VIP) for Fast & Efficient Verification
Verification IP Nov 25, 2015 Jason Polychronopoulos pdf
UVM Framework – Create a UVM Environment in Less than an Hour
UVM Framework Nov 25, 2015 Bob Oden Webinar
Leveraging Verification IP (VIP) for Fast & Efficient Verification
Verification IP Nov 25, 2015 Jason Polychronopoulos Webinar
UVM Framework – Create a UVM Environment in Less than an Hour
UVM Framework Nov 25, 2015 Bob Oden pdf
Creating UVM Testbenches for Simulation & Emulation Platform Portability
Acceleration Nov 24, 2015 Hans Van Der Schoot pdf
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
Debug Nov 01, 2015 Eric Rentschler - Siemens Eda Article

September 2015

Low Power Verification Techniques
Low Power Sep 23, 2015 Ellie Burns Webinar

July 2015

Unleashing the Full Power of UPF Power States
Low Power Jul 17, 2015 pdf
New School Connectivity Checking
Formal Verification Jul 01, 2015 Mark Eslinger Webinar

June 2015

Understanding Low Power Impact on CDC Logic
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Describing Low Power Logic with UPF
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Integrating Power Aware CDC into a Design Flow
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Questa CDC Power Aware
Clock-Domain Crossing Jun 30, 2015 Kurt Takara Session
Formal and Assertion-Based Verification of MBIST MCPs
Assertions Jun 06, 2015 Ajay Daga - Fishtail Design Automation Article
Starting Formal Right from Formal Test Planning
Formal Verification Jun 06, 2015 Jin Zhang Article
Emulation Based Approach to ISO 26262 Compliant Processors Design
Functional Safety Jun 06, 2015 David Kaushinsky - Siemens Eda Article
AutoCheck: Push-Button Bug Hunting
Formal Verification Jun 05, 2015 Mark Eslinger Session

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

Verification IP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

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