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osmosis 2022 (23)

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IEEE 1801 (17)

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osmosis Europe 2025 (15)

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osmosis 2023 (14)

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Automotive Functional Safety Forum (10)

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Israel Static & Formal Tech Day (7)

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VA Live 2023 - Huntsville (7)

VHDL-2008 (7)

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Low Power Verification Forum (5)

MARLUG 2023 (5)

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March 2016 - Volume 12 Issue 1 (5)

Mixed-Signal Verification (5)

Operators (5)

PSL (5)

Post-silicon Debug (5)

Postsim (5)

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Power Estimation (5)

Power Logic (5)

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QVIP Configurator (5)

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UCDB (5)

UCIe (5)

UVM Forum (5)

VA Live 2023 - Westford (5)

VA Live 2024 - El Segundo (5)

VA Live 2024 - San Diego (5)

VA Live 2025 - El Segundo (5)

VA Live 2025 - Hudson (5)

VIQ (5)

X-Effects (5)

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C++ (4)

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DAC 2019 (4)

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HBM (4)

HBM4 (4)

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Industry Trends (4)

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MBIST (4)

March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

Memory Usage (4)

Mitigation Architecture (4)

Multi-Die (4)

NVM Express (4)

OSCI (4)

PCIe Gen 6 (4)

PSS (4)

Parameterized Classes (4)

Portable Test & Stimulus (4)

QoR (4)

Reset Architecture (4)

SVTB (4)

Signal (4)

Static Analyses (4)

Sub-system Level (4)

Synergistic Verification (4)

Tessent Test Solutions (4)

UPF 4.0 (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Huntsville (4)

VA Live 2024 - Westford (4)

VA Live 2025 - Huntsville (4)

VA Live 2026 - El Segundo (4)

Validation (4)

Verification Architecture (4)

Voltage Domain Crossing (4)

Waivers (4)

Whats New in Functional Verification (4)

Wilson Research Group (4)

X-Aware (4)

ATPG (3)

Agentic Workflow (3)

Analysis Port (3)

Autonomous Systems (3)

Black Boxing (3)

Block Level (3)

Bounded Model Checking (3)

Breakpoint (3)

Built-In Self-Test (3)

Cache Coherency (3)

Checkpoint (3)

Clock Propagation (3)

Co-Verification (3)

Command API (3)

Context-Aware Debug (3)

Converters (3)

Coverage Exclusion (3)

Coverage Goals (3)

Cryptography (3)

Customization (3)

DDR (3)

Data Processing (3)

Data Types (3)

December 2017 - Volume 13 Issue 3 (3)

Design Constraints (3)

Design Cycle (3)

Design Hierarchy (3)

Design Scaling (3)

Development Environment (3)

Directed Test (3)

Dynamic Power (3)

ECO (3)

Error (3)

Error Injection (3)

Exhaustive (3)

FWHW (3)

Formal Methods (3)

Front and Back Door (3)

HDL Domain (3)

HLV (3)

Hardware Architecture (3)

Hardware Assurance (3)

Hardware Verification (3)

High-Speed (3)

IC Design (3)

IP Integration (3)

IP Security (3)

Initial States (3)

JEDEC (3)

July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

Mathematical Analysis (3)

Memory Models (3)

Multi-Core Architectures (3)

Namespaces (3)

Objectives (3)

October 2012 - Volume 8 Issue 3 (3)

Parallel Simulation (3)

Power Architecture (3)

Processor Core Verification (3)

Protocol Checkers (3)

Python (3)

QFL (3)

RDC Design (3)

RTL Sign-Off (3)

RTL Verification (3)

Radiation Mitigation (3)

Risk Mitigation (3)

SSD (3)

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Scalable Verification (3)

Schematic Debug (3)

Simulink (3)

Specification (3)

Specification Driven Formal (3)

Spiral Refinement (3)

State Machine (3)

State Transitions (3)

Static Checks (3)

System Level (3)

Tcl/Tk (3)

Transfer Protocols (3)

Trends (3)

Trust Verification (3)

UALink (3)

UVMC 2.3.3 (3)

UVMC 2.3.4 (3)

Unified Coverage Database (3)

VA Live 2019 - Westford (3)

VA Live 2024 - Austin (3)

VA Live 2024 - Fremont (3)

Variable (3)

Verification Trends (3)

Virtual Interface (3)

osmosis 2023 A&D (3)

2D/3D (2)

5G (2)

ADAS (2)

AEH (2)

ARBM (2)

ASIL-C (2)

Abstract Specification (2)

Access Path (2)

Adaptive (2)

Affect Probability (2)

Application Lifecycle Management (2)

Architectural Verification (2)

Arrays (2)

BFMs (2)

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Bidirectional (2)

Bins (2)

Bit Flips (2)

Bounded Tasks (2)

Bug Detection (2)

C (2)

CDC Protocol (2)

CDC Signals (2)

CHI (2)

COCOTB (2)

Callbacks (2)

Campaign Management (2)

Certification (2)

Channel Detection (2)

Clock Bridge (2)

Clocking (2)

Clocking Verification Challenges (2)

Configuration Database (2)

Connections (2)

Control Logic (2)

Cover Properties (2)

Cover Statement (2)

Coverage Intent (2)

Critical Storage (2)

Cross Coverage (2)

Cutpoint (2)

DPPM (2)

DVCON 2021 (2)

DVFS (2)

Data Encryption (2)

Data Link (2)

Debug Methodology (2)

December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

Design Creation (2)

Design for Safety (2)

Digital Signal Processing (2)

Distributed Resource Management (2)

Elements List (2)

Ethernet (2)

FIT Rate (2)

Fabric (2)

Fault Detection (2)

Fault Model (2)

Fault Scenarios (2)

Flip-Flop (2)

Floating-Point Hardware (2)

Formal Simulation (2)

GLS (2)

GOMACTech (2)

Governance (2)

Graph-Based Stimulus (2)

Hallucination (2)

Hardening (2)

Hardware-Assisted Verification (2)

Heterogeneous (2)

IEEE (2)

IEEE 754 (2)

IP-XACT (2)

ISA (2)

Illegal Bins (2)

Implementation Model (2)

Implicit/Explicit (2)

In-Circuit Simulation (2)

Instance (2)

Instance Mapping (2)

Instantiate (2)

Intelligent Integration (2)

Interconnect Signals (2)

Jittering (2)

June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

LVS (2)

Level-shifter (2)

Lockstep (2)

Loggers (2)

Logic Cone (2)

MCPs (2)

MIPI (2)

Machine Readable Specification (2)

March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metastable (2)

Metric Validation (2)

Mixed-Signal Design (2)

Modules (2)

Monitor (2)

Multi-Language Environment (2)

Non-Determinism (2)

Object Oriented Programming (2)

Objects (2)

October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

Open Architecture (2)

PAM4 (2)

PCI-SIG (2)

PCIe Gen 7 (2)

PMHF (2)

Parameter (2)

Parameter-to-Signal (2)

Parameterized Tests (2)

Partitioning (2)

Pattern Splitting (2)

Point-to-Point Connections (2)

Polymorphism (2)

Power Profiling (2)

Power Reduction (2)

Precedence (2)

Profiling (2)

QCX (2)

Questa Design Solutions (2)

RDC Analysis (2)

RDC Violations (2)

RTL-Aware Design (2)

Re-targeting (2)

Reference Model (2)

Reset Handling (2)

Reset Value (2)

Retargeting Flow (2)

Runtime (2)

SFV (2)

SLM (2)

SPFM (2)

Scoreboard (2)

Security Vulnerabilities (2)

Shift Left (2)

Sign-Off Methodology (2)

Silicon Lifecycle Management (2)

Software-Driven Verification (2)

Spice (2)

Split Transactor (2)

State Preservation (2)

Static Formal (2)

Stimulus Free Verification (2)

Sub-system (2)

Substrate (2)

Successive Refinement (2)

Supply Chain (2)

Synthesizable (2)

System-in-Package (2)

TLM FIFOS (2)

Test Environment (2)

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Time Cone (2)

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UPF 2.0 (2)

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USB (2)

UVMC 2.3.0 (2)

UVMC 2.3.1 (2)

UVMC 2.3.2 (2)

Ultra Accelerator Link (2)

Universal Approximation (2)

Unreachability (2)

VA Live 2026 - Austin (2)

VRM (2)

Vectors (2)

Verification Cycles (2)

Verification Integrity (2)

Virtual Prototyping (2)

X-Mitigation (2)

X-Pessimism (2)

X-State (2)

osmosis 2024 A&D (2)

$display (1)

2.5D (1)

2.5DIC (1)

3PIP (1)

AHB (1)

AHB-Lite (1)

AOP (1)

APB (1)

API (1)

AXI (1)

Active Driver Tracing (1)

Address Space Management (1)

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Advance Your Verification Methodology (1)

Advanced UVM (1)

Agent (1)

Agentic AI Framework (1)

Agile Development (1)

Alternate Routing ID (1)

Analysis Components (1)

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Autonomous Vehicles (1)

BISR (1)

Back Pointers (1)

Batch and Debug (1)

Bi-Directional (1)

Block to Chip (1)

Break on Change (1)

Build Phase (1)

C-PHY (1)

CMA (1)

COTS (1)

CSD (1)

CSI (1)

CSI-2 (1)

CXL (1)

Case Statements (1)

Checklists (1)

Class Objects (1)

Clock Cycle (1)

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Code Example (1)

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Combinational Loops (1)

Component Measurement and Authentication (1)

Compute Express Link (1)

Config_db (1)

Connected Verification (1)

Control Paths (1)

Control Points (1)

Controller Area Network (1)

Counterexample (1)

Cover Property (1)

Coverage Achievement (1)

Coverage Models (1)

D-PHY (1)

DVCon 2026 (1)

DVCon Europe (1)

Data Corruption (1)

Design Specification (1)

Design.bin (1)

Determinism (1)

Deterministic Test (1)

DisplayPort (1)

Dual Domains (1)

Dynamic CDC (1)

ED-80 (1)

EMC (1)

Electronic Design Integration (1)

Elliptic Curve (1)

Embedded Analytics (1)

Embedded Software (1)

Emerging Trends (1)

Enterprise Debug and Analysis (1)

Execution Trace (1)

Factory (1)

Fault Coverage (1)

February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

Flash (1)

Formal Test Planning (1)

Formal Verification Apps (1)

Functional Monitoring (1)

GPU (1)

Generation (1)

Golden Model (1)

HDMI (1)

HSI (1)

HYCON (1)

Hierarchical Components (1)

Hierarchical Sequences (1)

Host Processor (1)

IC/ASIC (1)

IEC 62304 (1)

IP Integrator (1)

IP Quality (1)

In-Circuit Emulation (1)

In-System Test (1)

Integer (1)

Integration Level (1)

Interrupts (1)

Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

Logic Faults (1)

Low Latency (1)

MUX (1)

March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

Mathworks (1)

Measurement (1)

Memory BIST (1)

Memory Debug (1)

Model Context Protocol (1)

Model-Based Design (1)

Multi-Cycle Paths (1)

NAND (1)

NLP (1)

NRRs (1)

Non-Resettable Registers (1)

Non-Trivial Bug Escapes (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

Observer (1)

PCIe Gen 4 (1)

PHY (1)

Partitioned Compile (1)

Phases (1)

Phrase Configuration (1)

Portability (1)

Power Consumption (1)

Power Gating (1)

Pre-Silicon (1)

Productivity Gap (1)

Property Editor (1)

Prototyping (1)

QEMU (1)

QOS Processor (1)

RAM (1)

RDC Methodology (1)

RDMA (1)

RISC-V Verification Interface (1)

RNG (1)

RTL Emulation (1)

Re-Spins (1)

Receiver (1)

Recording (1)

Recurrent Neural Networks (1)

Release Notes (1)

Repair Architecture (1)

Reporting (1)

Reset Environment (1)

Reset Tree (1)

Respins (1)

Root Complex (1)

Run Monitor (1)

SA-EDI (1)

SATA (1)

SCE-MI (1)

SOTIF (1)

SPDM (1)

SPI (1)

SafeSPI (1)

Safety Monitoring (1)

Scenario Generation (1)

Security Asset (1)

Security Protocol and Data Model (1)

Semantics (1)

Sequencer (1)

Sequential Errors (1)

Sequential Optimization (1)

Signal Processing Domain (1)

Single Root-IO Virtualization (1)

Singleton (1)

Softmodel (1)

Software Layers (1)

Static CDC (1)

Static RDC (1)

Sub-Module (1)

Subscriber (1)

Supply Set (1)

Syntax (1)

Systemic Faults (1)

TBX (1)

TPU (1)

Test Compression (1)

Test Coverage (1)

Tool Confidence Level (1)

Tool Detection (1)

Tool Impact (1)

Trace Depth (1)

Transaction Layer (1)

Transactional Assertions (1)

Transactors (1)

Transmitter IP (1)

Tunneling (1)

UCIS (1)

UEC (1)

UPF 3.1 (1)

USB 3.0 (1)

USB 3.1 (1)

UVM Simulation (1)

UVM-MS (1)

UVMC 2.1.4 (1)

UVMC 2.2 (1)

UVVM (1)

Unary (1)

Unidirectional (1)

Use Models (1)

VA Live 2023 - El Segundo (1)

VC File (1)

VCMs (1)

VIP - 3.1 (1)

Values (1)

VbyOne (1)

Verbose (1)

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Verification Component (1)

Verification Run Manager (1)

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WRG (1)

Wall-Clock Run-Time (1)

X-Optimism (1)

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November 2019

UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf
UVM Connect 2.3.2 HTML
UVMC Nov 14, 2019 John Stickley tar
UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf

October 2019

Questa PropCheck GUI - Overview
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Cone of Influence
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Debug a Firing
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Properties Tab
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Property Editor
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Run Monitor/Details
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Schematic
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Source Window
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Run Formal
Formal Verification Oct 10, 2019 Mark Eslinger Demo

September 2019

Questa SLEC Fact Sheet
Formal Verification Sep 30, 2019 Nicolae Tusinschi link

August 2019

Assuring the Integrity of RISC-V Cores and SoCs
Formal Verification Aug 21, 2019 Nicolae Tusinschi pdf
A New Approach to Low Power Verification - Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava pdf
A New Approach to Low Power Verification: Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava - Siemens Eda Paper

July 2019

Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick Conference
Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick pdf
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide Conference
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide pdf
Deep Learning Accelerator Using HLS
High-Level Synthesis Jul 15, 2019 pdf
Veloce HYCON - OS-aware IP Development Solution
Acceleration Jul 12, 2019 pdf
Emulation to Prototype - What’s Eating Your Productivity?
Acceleration Jul 11, 2019 pdf
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification
Clock-Domain Crossing Jul 10, 2019 Kurt Takara Webinar
Gain a Design-to-Revenue Edge in FPGA & SoC Designs with a Full Deployment of CDC Analyses and Verification
Clock-Domain Crossing Jul 10, 2019 Kurt Takara pdf

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

Browse all Intermediate content in Siemens Verification Academy

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