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March 2016 - Volume 12 Issue 1 (5)

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March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

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PCIe Gen 6 (4)

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UPF 4.0 (4)

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VA Live 2023 - Austin (4)

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December 2017 - Volume 13 Issue 3 (3)

Design Constraints (3)

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July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

Mathematical Analysis (3)

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October 2012 - Volume 8 Issue 3 (3)

Parallel Simulation (3)

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UALink (3)

UVMC 2.3.3 (3)

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VA Live 2019 - Westford (3)

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VRM (3)

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December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

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IEEE (2)

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June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

LVS (2)

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March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metric Validation (2)

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October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

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VA Live 2026 - Austin (2)

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Controller Area Network (1)

Counterexample (1)

Cover Property (1)

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Coverage Models (1)

D-PHY (1)

DRAM (1)

DVCon 2026 (1)

DVCon Europe (1)

Data Corruption (1)

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Design.bin (1)

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ED-80 (1)

EMC (1)

Electronic Design Integration (1)

Elliptic Curve (1)

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Embedded Software (1)

Emerging Trends (1)

Enterprise Debug and Analysis (1)

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Execution Trace (1)

FPGA Development (1)

Factory (1)

February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

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Flash (1)

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IEC 62304 (1)

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Integer (1)

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Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

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March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

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Non-Resettable Registers (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

Observer (1)

PCIe Gen 4 (1)

Partitioned Compile (1)

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RAM (1)

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VA Live 2023 - El Segundo (1)

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XML (1)

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eFuse (1)

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June 2022

Questa Lint vs Formal AutoCheck
Questa Design Solutions Jun 15, 2022 Kevin Campbell Webinar
Questa Lint vs Formal AutoCheck
Questa Design Solutions Jun 15, 2022 Kevin Campbell pdf

May 2022

Verilog & VHDL Debug & Weeding
Debug May 18, 2022 Rich Edelman link
Siemens and the US Government - Mitigating Microelectronics Development Challenges
Functional Safety May 10, 2022 Rich Powlowsky Webinar
Bringing Model-based Systems Engineering to IC and FPGA Design
FPGA Verification May 10, 2022 Ray Salemi Webinar
From Model to Implementation with High-Level Synthesis
High-Level Synthesis May 10, 2022 Russell Klein Webinar
Accelerate Learning Curves and Achieve Program Goals Efficiently
Questa Design Solutions May 10, 2022 Chris Giles Webinar
How Automation Enables any RTL D&V Engineer to Run Exhaustive Formal Verification
Formal Verification May 10, 2022 Joe Hupcey Webinar
Accelerate Development Using Advanced Debugging Approaches
Debug May 10, 2022 Rich Edelman Webinar
Collaborative Verification Management & Coverage Analysis
Verification Management May 10, 2022 Darron May Webinar
System Level SoC Verification and Validation Using Emulation and Prototype Platforms
Acceleration May 10, 2022 Vijay Chobisa Webinar
Trust but Verify Your IP with Solido Crosscheck
Analog Mixed-Signal May 10, 2022 Felipe Schneider Webinar

April 2022

Clearing the Fog of ISO 26262 Tool Qualification
Functional Safety Apr 13, 2022 Jacob Wiltgen link

March 2022

System Verification with MatchLib
High-Level Synthesis Mar 31, 2022 Russell Klein mp4
System Verification with MatchLib
High-Level Synthesis Mar 31, 2022 pdf
Key Findings of a Safety Critical Lifecycle Evaluation
Functional Safety Mar 25, 2022 Trey Reeser - Siemens Eda link
Modeling Analog Devices using SV-RNM
Analog Mixed-Signal Mar 23, 2022 pdf
Estimating Power Dissipation of End-User Application on RTL
Low Power Mar 23, 2022 mp4
How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Formal Verification Mar 23, 2022 Mark Eslinger pdf
How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Formal Verification Mar 23, 2022 Mark Eslinger pdf
How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Formal Verification Mar 23, 2022 Mark Eslinger mp4
UVM-AMS - An Update on the Accellera UVM
UVM - Universal Verification Methodology Mar 23, 2022 mp4
Modeling Analog Devices using SV-RNM
Analog Mixed-Signal Mar 23, 2022 mp4
Why Not Connect Using UVM Connect: Mixed Language Communication Got Easier with UVMC
UVMC Mar 23, 2022 Vishal Baskar mp4
Why Not Connect Using UVM Connect: Mixed Language Communication Got Easier with UVMC
UVMC Mar 23, 2022 Vishal Baskar pdf

New White Papers

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DVCon India 2026

September 1st - September 3rd

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DVCon Taiwan 2026

Tuesday, September 8, 2026

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DVCon Japan 2026

Thursday, September 10, 2026

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