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September 2021 - Volume 17 Issue 2 (7)

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December 2019 - Volume 15 Issue 3 (3)

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Show Less

November 2022

Part 7: IC/ASIC Design Trends
Planning, Measurement and Analysis Nov 28, 2022 Harry Foster link
Part 6: FPGA Language and Library Trends
Planning, Measurement and Analysis Nov 21, 2022 Harry Foster link
Functional Verification Study - 2022
Planning, Measurement and Analysis Nov 16, 2022 Harry Foster Webinar
Part 5: FPGA Verification Technology Adoption Trends
Planning, Measurement and Analysis Nov 13, 2022 Harry Foster link
Part 4: FPGA Verification Effort Trends (Continued)
Planning, Measurement and Analysis Nov 06, 2022 Harry Foster link
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai Webinar
Questa Design Solutions as a Sleep Aid
Questa Design Solutions Nov 02, 2022 Vinayak Desai pdf

October 2022

Part 3: FPGA Verification Effort Trends
Planning, Measurement and Analysis Oct 30, 2022 Harry Foster link
CDC and RDC Assist: Applying machine learning to accelerate CDC analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma pdf
CDC and RDC Assist: Applying Machine Learning to Accelerate CDC Analysis
Questa Design Solutions Oct 25, 2022 Atul Sharma Webinar
Formal and the Next Normal
Formal Verification Oct 19, 2022 Joe Hupcey Webinar
Dig a Pool of Specialized SystemVerilog Classes
SystemVerilog Oct 17, 2022 Chris Spear link
Part 1: The Global FPGA Semiconductor Market
Planning, Measurement and Analysis Oct 16, 2022 Harry Foster link

September 2022

Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Verification IP Sep 21, 2022 Gordon Allan Webinar
SystemVerilog: Implicit handles
SystemVerilog Sep 06, 2022 Chris Spear link

August 2022

SystemVerilog: Class Member Visibility
SystemVerilog Aug 29, 2022 Chris Spear link
UVM Framework Release 2022.3
UVM Framework Aug 15, 2022 Bob Oden tar

July 2022

The Democratization of Digital Methodologies for AMS Verification
Analog Mixed-Signal Jul 05, 2022 Sumit Vishwakarma Article
Getting to Know Visualizer - Part II
Debug Jul 05, 2022 Rich Edelman Article
Unblocking the Full Potential of SSDs Using Zoned and Key Value Namespaces
Verification IP Jul 05, 2022 Himani Kaushik - Siemens Eda Article
Reflections on Users’ Experiences with SVA - Part II
SystemVerilog Jul 05, 2022 Ben Cohen Article
Easy Testbench Speedups
SystemVerilog Jul 05, 2022 Eileen Hickey - Doulos Inc. Article

June 2022

The Three Pillars of Intent-Focused Insight
Planning, Measurement and Analysis Jun 08, 2022 Harry Foster Webinar

May 2022

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
UVM Framework May 10, 2022 Bob Oden Webinar
Securing the Electronics Development Chain with IC Integrity Solutions
Formal Verification May 10, 2022 John Hallman Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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