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As I write this, I'm sitting in an airplane on my way to Denver, and I find myself thinking about "productivity." The first thought that came to my mind was whether I wanted to pay $8 to watch TV on the flight (not a movie, mind you – just television) or would be better off spending my time productively by writing this note. You can tell which path I chose.

Another thought that occurred to me, given my destination, was the recent comeback of NFL quarterback Peyton Manning who, after missing all of last season due to several neck surgeries, now plays for the Denver Broncos.1 As a die-hard New England Patriots fan, I, like many other Patriots fans, have developed a "love-hate" relationship with Manning. For many years his Indianapolis Colts team was the nemesis of my Patriots and the comparisons between Manning and Tom Brady, the Patriots' quarterback, were constant. Depending on what metric you chose, a case could be made that either one is better, and possibly the greatest of all time.

Ah, metrics! There is no substitute for clear, objective data when evaluating a player, or a process for that matter. A productive quarterback is measured most of all on how many times he wins, especially in the Super Bowl (advantage: Brady), but there are other metrics that can be used as well. For verification, productivity really comes down to being able to reliably determine if your chip will run correctly as efficiently as possible. Just as the quarterback with the better completion percentage doesn't always win, verification productivity is about much more than just how fast your simulator runs a particular test. We must think about the full spectrum of verification tasks and the tools and technology available to apply to them. Just as a football game is ultimately determined by the final score, all that matters to us as verification engineers is how well we can determine the correctness of our design within the schedule allotted. Keep these thoughts in mind as you read this month's issue of Verification Horizons.

Our featured article this month comes from our friends at ST Ericsson. In "ST-Ericsson Speeds Time To Functional Verification Closure With Questa Verification Platform," you'll see a case study of their experience adopting Questa to get a handle on their verification process. The complexity of their chip demanded a mix of tools, including simulation and static (formal) analysis for clock-domain-crossing verification, and you'll see that Questa's UCDB and Verification Management suite of tools gave them what they needed.

Static verification is becoming much more mainstream as a complement to simulation, and our next article, "The Top Five Formal Verification Applications," shows why. It used to be that static verification meant formal model checking of hand-coded properties, which typically required a PhD to run. Over the past few years, however, we've focused on somewhat narrower applications that automate specific parts of the verification process and greatly simplify the use model. If you find yourself running into any of the problems on this list, you should probably consider applying static verification.

A good football team needs to play well on both offense and defense, and development of a successful SoC requires the design and verification teams to work together. In "Three Steps to Unified SoC Design and Verification" my colleagues Shabtay Matalon and Mark Peryer share their "game plan" for system-to-RTL design and verification. Making the appropriate tradeoffs at the system level to achieve power and performance goals and reusing system level and RTL models together throughout the flow is an ideal environment with many advantages. Adopting these steps will help you achieve a repeatable and measurable flow to address all aspects of SoC development.

Staying with the idea of power for a moment, our next article outlines the "Evolution of UPF" through its many stages of standardization in Accellera and IEEE and discusses some of the enhancements coming in the new 2.1 release. Erich Marschner, one of the leaders of the UPF standardization effort, shows you how power management techniques have advanced over the years and how the UPF standard (IEEE 1801) has been updated to keep pace. Since low power design is such a critical piece of so many chips being designed today, you may want to see what's in store.

If you have any analog circuitry on your chip, "Improving Analog/Mixed-Signal Verification Productivity" is a must read. As many of you have experienced, analog may be a small part of your chip, but it is often the key differentiator for you. That makes the fact that it is often the cause of most of your problems particularly troublesome. In this article you'll learn an approach that lets you combine analog and digital in your design and, most importantly, verify that they'll work correctly together.

Last but not least, our Consultants' Corner article is supplied this month by Jim Lewis, a long-time VHDL trainer, who shares his thoughts on "VHDL-2008: Why it Matters." For you VHDL users out there, this will serve as a great introduction to these important new features that will let you be more efficient, effective and productive in writing both your RTL and testbench code in VHDL.

At press time, Peyton Manning has one win and one loss with the Broncos. It's obvious that his passion for the game has not diminished and his intellectual ability on the field is a sight to behold. It's not clear if he's physically up to the standards he set over the years, but as long as he's not playing the Patriots (or negatively affecting their playoff chances), I'll root for him. It's great to see someone use all of the tools at his disposal and dedicate himself to making his team successful. For that reason, I'll be rooting for you on your next project, too.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons