by Erich Marschner, Product Manager, Questa Power Aware Simulation, Mentor Graphics
Power management is a critical aspect of chip design today. This is especially true for chips designed for portable consumer electronics applications such as cell phones and laptop computers, but even non-portable systems are increasingly optimizing power usage to minimize operation costs and infrastructure requirements. Power management requirements must be considered right from the beginning, and the design and implementation of power management must occur throughout the flow, from early RTL design on through physical implementation. Verification of the power management logic is also essential, to ensure that a device operates correctly even when the power to various subsystems or components is turned off or varied to optimally meet operating requirements.
Hardware description languages such as Verilog, VHDL, and SystemVerilog focus on functionality and timing. They were not designed to enable specification of power management. In fact, hardware description languages basically assume that power is always on, and that all parts of a system operate concurrently at all times. So trying to represent power management concepts using a hardware description language doesn't work.
This is where IEEE Standard 1801, the Unified Power Format (UPF) comes into play. UPF gives designers a way of specifying how power to a chip can be managed in a given implementation. The specification is separate from the HDL source, so that the HDL can be reused in different contexts with different power management requirements. This also allows for experimentation regarding power management approaches without having to modify the golden RTL. And since UPF can be used by both verification tools and implementation tools, a power management specification written in UPF can be used throughout the flow, from early RTL verification through synthesis, test insertion, and place & route, as the RTL code is transformed to a Gate Level netlist and is further modified during backend implementation.
UPF is no longer new; the standard was first published in 2007. Since then, several versions of the UPF standard have been developed, as UPF has evolved to support increasing requirements for power management and a better understanding of the challenges and methodologies involved. The latest version of the standard is in the final stages of development and should be out early in 2013.
This article gives a high level overview of the concepts and capabilities that UPF provides and how those concepts and capabilities have evolved over the past few years. It also gives a preview of what is coming in the next version of UPF.
A few years and several technology generations ago, power management required little more than turning off the clock of a functional unit when it did not need to operate. In those days, most of the power used by a system was consumed by the clock tree, and gating the clocks for unused blocks produced significant power savings. But as device technology generations became smaller and smaller, and especially at technology nodes lower than 65 nm, static leakage has become the dominant factor in energy loss.
While we still need to do clock gating to manage power, in today's chips we also need to do power gating and other types of power control as well in order to minimize static leakage.
Power gating requires that a design be partitioned into groups of cells, called power domains, that have the same power requirements, so they can all be powered by the same power supply. A chip may have many different power domains, each with its own power supply. When a given power domain is not required, the clock for that power domain can be turned off, and its power supply can be turned off as well.
If the state of the power domain needs to be saved while it is powered down, retention registers can be inserted in place of normal registers. These retention registers allow information that cannot be recomputed easily or quickly to be saved and restored when the domain is powered up again. To ensure that state is saved properly before power down and restored properly before power up, an appropriate sequence of power control signals must be used when powering down a domain and powering it up again later.
Turning off a power domain minimizes static leakage, but it also creates another problem: the outputs of the domain may float to unpredictable values, which could cause unexpected changes on inputs to other domains that are still powered on. To address this, isolation cells are inserted at power domain boundaries, so that when the driving domain is powered down, an isolation cell can "clamp" the domain's no-longer-driven output to a known value that will not adversely affect any downstream power domain.
Static leakage can also be reduced by reducing voltage for a given power domain without actually turning off the power supply. Low voltage states can be used for state retention if care is taken to ensure that the inputs to a domain in such a low voltage state do not toggle. This is another application for isolation cells, in this case on the inputs to the domain rather than the outputs.
Since voltage level also affects performance, a chip may be designed to use different voltages in different domains, depending upon respective performance requirements, or may be designed to change the voltage in a given domain as performance requirements vary over time. This creates a need for translating signals from one voltage to another, as the output of one domain at a given voltage level goes to the input of another domain at another voltage level. Power management cells called level shifters are inserted to do this translation.
All of the above structures are involved in managing changes in the power supplied to different parts of the chip. The chip also needs structures for providing and distributing power to each of the power domains. Power supply networks are ultimately built in the physical implementation of the chip via cell abutment and various techniques for power switching. For early verification, the power distribution network can be modeled as a set of supply ports, supply nets, and abstract power switches that rout power from the top-level interface of the chip down to each power domain.
The first version of UPF was developed by Accellera, based upon power aware simulation technology donated by Mentor Graphics. Based on Tcl, this standard provided commands for defining the power management structures required for a given design, to enable power aware verification and to drive power management implementation. For example, the UPF 1.0 commands for creating a power domain and creating the supply network for a power domain look like this:
To define a power domain:
To define the supply network:
UPF 1.0 introduced the notion of strategies for adding isolation, retention, and level shifting features to a design under power management. Each strategy defines a rule for inserting isolation or level shifting for a given port on the boundary of a power domain, or for inserting retention registers in place of normal registers within a power domain. For isolation and retention, which require control signals to enable, additional commands were provided to allow the user to specify those control signals. Following are the commands and primary options used for defining such strategies:
To add isolation at domain boundaries:
set_isolation <strategy name> -domain
set_isolation_control <strategy name> -domain
To add retention within a domain:
set_retention <strategy name> -domain
set_retention_control <strategy name>
-domain –save_signal –restore_signal
To add level shifting at domain boundaries:
set_level_shifter <strategy name> -domain
Additional options provided more details about exactly where isolation, retention, and level shifting cells were to be inserted, how they should be powered, and where they should be placed in the design.
UPF 1.0 focused on individual supply nets and their on/off states. This approach had some limitations, largely because it did not reflect the fact that supply nets come in pairs – power and ground. Also, UPF 1.0 had built-in semantics for how signals should be corrupted when a power domain is turned off. Although UPF 1.0 did allow a power intent specification to be partitioned into multiple files, it had limited support for hierarchical composition of power intent specifications, which made it more difficult to use for largescale SoC designs. Nonetheless, UPF 1.0 has been used successfully for many designs in the past five years, and until recently most users were still using low power design and verification flows based on the UPF 1.0 standard.
The second version of UPF was developed in the IEEE. Based upon Accellera UPF 1.0, IEEE Std 1801 UPF adds new concepts and new features to enable much more flexible specification, verification, and implementation of power aware designs. The second version was approved by the IEEE in March 2009.
UPF 2.0 defines the concept of supply sets, which are a collection of supply nets that provide a complete power supply. These include the power and ground supplies as well as optional bias supplies that may be used to provide more precise control over the power used by the transistors in a given cell.
Supply sets provide two major advantages. First, they greatly simplify modeling of the supply distribution network. Instead of creating and connecting all of the individual supply ports and nets, a user can more easily create a supply set and share it among multiple power domains or power management cells. Second, they allow the user to define exactly how a given power domain's cells respond to a particular change in the power supplied to that domain. As a result, UPF 2.0 is able to model not only on/off states, but also various bias states that reflect different intermediate levels of corruption—and all of this is under the user's control. This enables use of UPF to model a variety of more sophisticated power management structures and techniques used in today's designs.
Another new concept in UPF 2.0 is the notion of successive refinement of UPF power intent specifications. This concept stems from the fact that power-related information about the design may be developed incrementally over time, by different people, just like the design itself. IP blocks may have power management constraints defined for them, such as the isolation clamp value for each input port, if this IP block is used in a system in which the drivers of those inputs can be powered down. In contrast, information about where isolation will actually be inserted, how it will be controlled, and how it will be powered may not be available until the IP block is actually instantiated in a larger system. In UPF 2.0, commands such as create_power_domain, set_isolation, etc. have been extended to allow power intent information for a given power domain to be specified incrementally, so that a complete power intent specification can be composed from information provided by both block designers and system designers. This supports a hierarchical composition methodology that greatly facilitates use of UPF 2.0 in the context of complex systems.
One of the most substantial additions to UPF 2.0 is the command add_power_state, which allows the user to define power states for supply sets and power domains. This command replaces the UPF 1.0 power state table commands, which provided a very simple way of representing the possible power states of a system. With add_power_state, successive refinement and hierarchical composition can now be used to build up a complete model of the power states of a system, and the simulation semantics for each power state can be defined independently.
Adoption of UPF 2.0 did not occur widely at first due to limited support for it in EDA tools. However, in the past year, most users have been at least looking into moving up to UPF 2.0, and some are moving rapidly to adopt these new features. The adoption rate will almost certainly increase as EDA vendors complete their support for UPF 2.0 features.
For the past several years, the IEEE P1801 working group has been developing the next version of the UPF standard. The working group now includes all major EDA vendors and a large number of UPF users, representing quite a cross-section of the industry. In fact, the UPF working group has the broadest user participation of any EDA standard ever developed by the IEEE, which says a lot about the importance of low power design in the industry today.
Although many users are just beginning to adopt UPF 2.0, the working group continues to focus on refining and improving the standard. For UPF 2.1, the working group's goals have been primarily to clarify and correct any ambiguities or problems with the existing UPF 2.0 definition, and to make minor enhancements to improve usability of the standard. This includes deprecation of some of the older UPF 1.0 commands that have been replaced with better commands in UPF 2.0, as well as a lot of work on definitions and presentation of concepts to make the intended meaning and usage of UPF commands more clear to users.
UPF 2.1 will also contain a few significant enhancements. One of these is definition of the concept of supply net and supply set equivalence, which will enable simpler and more flexible specification of power intent based on electrical and functional equivalence of supplies instead of strict equivalence by name. Related areas of improvement include clarifications regarding the semantics of buffer (repeater) insertion, isolation and level shifting insertion, retention register structures and controls, and guidance regarding the use of add_power_state for modeling system power states. New commands for modeling power management cells have also been added.
The UPF 2.1 definition is almost completed at this point. It is expected to go into ballot for industry approval in October 2012. IEEE approval is expected to occur in March 2013, with publication to follow shortly thereafter.
Low power design is here to stay—it is a critical aspect of every chip design today. IEEE Standard 1801 UPF is the notation that enables low power design and verification in the context of a conventional HDL-based design flow. And just as design and implementation techniques continue to evolve over time, UPF is also continuing to improve over time, to meet the needs of design and verification engineers concerned with power management.
UPF is supported today by many of Mentor Graphics' products, including Questa Power Aware Simulation (PASim), Olympus, Veloce, Tessent, and Calibre. If you are interested in how these tools support and make use of UPF power intent specifications, contact the corresponding product managers for more information.
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