by Rachida El IDRISSI, ST-Ericsson
Functional verification is one of the most critical steps in the IC development cycle. As complexity increases, along with the associated cost of fixing late-stage functional defects, manufacturers including ST-Ericsson are putting additional effort into the up-front verification process.
As is true in many engineering projects, the most difficult step in verification is knowing when you are done. The challenge of reaching verification closure stems mostly from increasing complexity. Recall that as a general rule of thumb, verification cycles rise at some multiple to the number of gates in a design, which is enough to give one pause in the age of billion-gate designs. Other obstacles on the