An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench

FPGA designs are becoming too large to verify by visually checking waveforms, as the functionality has become beyond easy comprehension.

DUT-TB
FPGA Designs
RTL
Stimulus
Testbench
Test Environment
UVM
VHDL
March 2016 - Volume 12 Issue 1
Verification Horizons
Beginner

UVM - Universal Verification Methodology

Shaela Rahman - Baker Hughes

DUT-TB
FPGA Designs
RTL
Stimulus
Testbench
Test Environment
UVM
VHDL
March 2016 - Volume 12 Issue 1
Verification Horizons
Beginner

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