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• Redefining Static and Formal Verification (Paper)
• Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification (Webinar)
• Reducing Area & Power Consumption with Formal-based ‘X’ Verification (Webinar)
• Reetika (author)
• Reflections on Users’ Experiences with SVA (Article)
• Reflections on Users’ Experiences with SVA - Part II (Article)
• Register Adapters, Predictors and Tests (Session)
• Register Check: Memory Mapped Register Verification (Session)
• Register Layer Adapter (Chapter)
• Register Model & Structure (Chapter)
• Register Model Coverage (Chapter)
• Register Model Generation and Integration (Session)
• Register Model Generation and Replacement (Session)
• Register Modeling: Exploring Fields, Registers and Address Maps (Paper)
• Register Package (Chapter)
• Register Sequence Examples (Chapter)
• Register Verification: Do We Have Reliable Specification? (Paper)
• Register-Based Testing (Session)
• Register-Level Functional Coverage (Chapter)
• Register-Level Scoreboards (Chapter)
• Register-Level Stimulus (Chapter)
• Relieving the Parameterized Coverage Headache (Article)
• Reporting (Session)
• Reporting Verbosity (Chapter)
• Requirement Tracing in the ISO 26262 World (Webinar)
• Requirements Writing Guidelines (Chapter)
• Reset Verification in SoC Designs (Article)
• Reset-Domain Crossing (topic)
• Reset-Domain Crossing Overview & Questa RDC Methodology (Webinar)
• Resolving Metastability Issues for Multi-clock SoC Environment for I2C (Article)
• Resolving the Limitations of a Traditional VIP for PHY Verification (Article)
• Results Checking Strategies with Portable Stimulus (Article)
• Reusable Coverage, Reporting, and Options (Lesson)
• Reusable UPF: Transitioning from RTL to Gate Level Verification (Article)
• Reusable Verification Framework (Article)
• Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation (Article)
• Rich Edelman (author)
• Rich Powlowsky (author)
• Rick Koster (author)
• Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project (Article)
• Rohit Jain (author)
• Ronen Shoham (author)
• Running Simulations (Session)
• Russell Klein (author)
• SATA Specification 3.3 Gaps Filled by SATA QVIP (Article)
• SLEC Introduction (Session)
• SLEC for Bug Fix / ECO (Session)
• SLEC for Design Optimization (Session)
• SLEC for Low Power Clock Gating (Session)
• SLEC for Safety Mechanism (Session)
• ST-Ericsson Speeds Time to Functional Verification Closure with Questa (Article)
• SVA Alternative for Complex Assertions (Article)
• SVA in a UVM Class-based Environment (Article)
• SVUnit Case Studies & Summary (Session)
• Safety Analysis for Automotive Chips Based on ISO 26262 (Webinar)
• Sampling and Using Coverage (Lesson)
• Sanjay Gupta (author)
• Satish Banukumar (author)
• Saving Time and Improving Quality with a Specification to Realization Flow (Article)
• Scoreboards (Chapter)
• Scoreboards and Predictors (Session)
• SecureCheck: How Secure is your Design? (Session)
• Securing Next-Generation Interconnects: PCIe® Gen7 Security Verification (Webinar)
• Securing the Electronics Development Chain with IC Integrity Solutions (Webinar)
• Securing your FPGA Design from RTL through to the Bitstream (Webinar)
• Selecting a Portable Stimulus Application Focal Point (Article)
• Selective Radiation Mitigation for Integrated Circuits (Paper)
• Self-Checking Testbenches (Session)
• Semaphores and Mailboxes (Lesson)
• Separate Top-Level Modules (Chapter)
• Separating Test Intent from Design Details with Portable Stimulus (Article)
• Sequence API (Chapter)
• Sequence Categories (Session)
• Sequence Driver Connection (Chapter)
• Sequence Library (Chapter)
• Sequence Priority (Chapter)
• Sequence, Sequence on the Wall: Who's the Fairest of Them All? (Paper)
• Sequence-Driver Use Models (Chapter)
• Sequences (Chapter)
• Sequences and Tests (Session)
• Sequential Logic Equivalence Checking (track)
• Set Breakpoints and Single Step Debug (Demo)
• Setting Up the Register Layer (Session)
• Seven Separate Sequence Styles Speed Stimulus Scenarios (Paper)
• Shantanu Samant (author)
• Shift Left using AutoCheck Formal Verification (Conference)
• Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP (Webinar)
• Should I Kill My Formal Run? Part 1: Formal Run is In-Progress (Webinar)
• Should I Kill My Formal Run? Part 2: Avoid Trouble and Set Yourself Up For Success (Webinar)
• Shubhankar Deshmukh (author)
• Siemens EDA FuSa Flow for Achieving an ASIL-C Safety Architecture (Paper)
• Siemens EDA has Accellera's Latest Standard Covered (Article)
• Siemens and the US Government - Mitigating Microelectronics Development Challenges (Webinar)
• Similar but Different: The Tale of Transient and Permanent Faults (Paper)
• Simplified UVM for FPGA Reliability: UVM for “Sufficient Elemental Analysis” in DO-254 Flows (Article)
• Simplifying Assertion Validation Using UVM Callbacks (Article)
• Simplifying Generation of DO-254 Compliant Verification Documents for AEH Devices (Article)
• Simplifying HDCP Verification Using Questa Verification IP (Article)
• Simplifying Mixed-Signal Verification (Article)
• Simplifying Questa Usage and Deployment with Qrun (Webinar)