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Improving Verification Productivity Using Questa One Sim

Webinar - Oct 23, 2025 by Karim Ameziane

This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim. Furthermore, the webinar will showcase Questa One Sim's cutting-edge debugging tools. Experience how advanced capabilities like Protocol Debug, and X-Debug enhance productivity, enabling you to find bugs faster.
Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

Webinar - Oct 15, 2025 by Justin Bunnell

In this webinar, you will be introduced to the UALink protocol, focusing on its architecture and key features that enable scalable AI systems. We will then dive into the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.
Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

Webinar - Oct 08, 2025 by Kirolos Magdy

In this webinar, through practical demonstrations and real-world examples, you'll see how next-generation verification goes beyond traditional approaches - enabling teams to break down silos, accelerate design cycles, and achieve higher quality results through intelligent automation and collaborative workflows.
Did You Know QuestaSim Supports VHDL-2019?

Webinar - Oct 01, 2025 by Abdelrahman Tharwat

In this webinar, we will explore the VHDL-2019 supported features in QuestaSim such as; enhancing your VHDL testbench, accessing the host environment, assertion reporting, view modes for design configuration optimization and more.
From Novice to Expert: Your Tutorial Roadmap at DVCon Europe 2025

Resource (Verification Horizons Blog) - Sep 17, 2025 by Joe Hupcey

In support of Verification Academy’s educational mission, Siemens is either directly sponsoring or contributing to the following five tutorials at the upcoming DVCon Europe 2025 on Tuesday, October 14th.
No Reset? No Worries! Smarter Ways to Tackle RDCs to NRRs

Resource (Verification Horizons Blog) - Sep 16, 2025 by Reetika

As system-on-chip (SoC) designs continue to evolve, they’re not just expanding in size—they’re growing in complexity. Among the many challenges this evolution brings, one of the most subtle yet critical is the handling of resets. Modern architectures often juggle multiple asynchronous reset sources along with sequential elements, such as non-resettable registers (NRRs), which operate without dedicated reset pins.
Class is Back in Session this October: Verification Academy’s Cutting-edge Weekly Webinar Series

Resource (Verification Horizons Blog) - Sep 16, 2025 by Joe Hupcey

Verification Academy’s fall semester starts this October with the following series of weekly deep dive webinars.
Functional Verification Insights: A Conversation with Abhi Kolpekwar

Resource (Verification Horizons Blog) - Sep 15, 2025 by Harry Foster

Over the years, I’ve had the privilege of sharing industry data and analysis through the Siemens EDA & Wilson Research Group Functional Verification Studies . Those findings help us understand the challenges our industry faces—rising complexity, resource pressures, and declining first-silicon success rates.
The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy.

Resource (Verification Horizons Blog) - Sep 08, 2025 by Rich Edelman

The grapes have returned – this weekend was “harvest” time. Jelly everywhere. A lot like this year here at Siemens. Lots of activity. New products. Announcements. Products everywhere. Jelly everywhere.
Why First-Silicon Success Is Getting Harder for System Companies

Resource (Verification Horizons Blog) - Sep 03, 2025 by Harry Foster

Everyone wants their own chip. Few are hitting first-silicon success. That’s the paradox shaping today’s semiconductor landscape. In the 2024 Siemens EDA / Wilson Research Group Functional Verification Study , which I authored, we found that only 14% of ASIC/SoC projects achieved first-silicon success — the lowest figure in more than twenty years of tracking this data.
Siemens at DVCon India 2025: Driving the Future of Design and Verification

Resource (Verification Horizons Blog) - Aug 26, 2025 by Dennis Brophy

DVCon India 2025 , taking place on September 10–11 at the Radisson Blu, Marathahalli, Bangaluru , will mark a special milestone—its 10th anniversary . Over the past decade, DVCon India has grown into one of the region’s most influential conferences for design and verification professionals. Siemens will be prominently featured across vision talks, technical papers, posters, and workshops, showcasing its leadership in AI-driven EDA, hardware-assisted verification, and formal methodologies.
Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!

Resource (Verification Horizons Blog) - Aug 25, 2025 by Dave Rich

The DVCon U.S. 2026 Call for Papers deadline is Sunday, September 7th at 11:59 PM . Don’t miss your chance to share your expertise and help shape the future of design and verification.
SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment

Paper - Aug 20, 2025 by Rich Edelman

Transaction level modeling and transaction level debug have been in use for years in SystemVerilog and Verilog simulation and verification, but not as available in VHDL, perhaps not used in GLS simulation and C testbenches, and taking new forms in system level modeling. This paper re-introduces and refreshes transaction recording and debug and suggests how each abstraction level can be used productively with worked examples runnable by the reader.
SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment

Resource (Paper (.PDF)) - Aug 20, 2025 by Rich Edelman

This paper re-introduces and refreshes transaction recording and debug and suggests how each abstraction level can be used productively with worked examples runnable by the reader.
SystemVerilog Transactions, UVM and C: Correlation in a Functional Verification Environment

Resource (Slides (.PDF)) - Aug 20, 2025 by Rich Edelman

This paper will review the various APIs and methods for transaction recording and demonstrate the concepts using an example. That example can be reused in reader code and is open source.
Verifying the Evolving UCIe Landscape: A 3.0-Aware Architecture for Manageability and Beyond

Resource (Paper (.PDF)) - Aug 13, 2025 by Prashant Dixit

With integrated debug hooks, exhaustive protocol checkers, traceability mechanisms, and topology-agnostic test scenarios, Avery UCIe VIP ensures functional correctness and architectural compliance. The architecture imposes no constraints on the DUT, enabling verification of any component within the management domain. Additionally, Avery UCIe VIP is equipped to handle the new demands introduced by UCIe 3.0, ensuring readiness for next-generation chiplet systems.
Accelerating UCIe Multi-die Verification with a Scalable, Smart Framework

Resource (Paper (.PDF)) - Aug 13, 2025 by Ujjwal Negi

Multi-die architecture introduces layers of verification complexity along with protocol-level challenges. Questa One Avery VIP for UCIe provides a protocol-aware, layered verification framework that scales from block-level validation to full system-level testing. Its automation capabilities enable faster set up and targeted testing across diverse DUT configurations. Integrated debugging tools provide high observability and faster root-cause analysis.
Accelerating UCIe Multi-die Verification with a Scalable, Smart Framework

Paper - Aug 13, 2025 by Ujjwal Negi

The Avery UCIe VIP provides a highly efficient and customizable verification environment, significantly reducing the effort and time needed. With automatic testbench generation, users can move from environment setup to actual verification almost instantly. The combination of configurable APIs, protocol-aware callbacks, and flexible parameter controls gives users complete control to simulate and reproduce any scenario, including complex corner cases, without rewriting their environment.
Verifying the Evolving UCIe Landscape: A 3.0-Aware Architecture for Manageability and Beyond

Paper - Aug 13, 2025 by Prashant Dixit

This white paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One™ Avery™ VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table set up for both direct and indirect management paths.
Siemens EDA at FMS 2025 – Shaping the Future of Memory and Storage

Resource (Verification Horizons Blog) - Jul 31, 2025 by Dennis Brophy

Siemens EDA is proud to be a featured participant at the Future of Memory and Storage (FMS) 2025 conference, taking place at the Santa Clara Convention Center . As a leader in verification IP and system-level solutions, Siemens EDA will showcase cutting-edge innovations across CXL, UCIe, NVMe, and AI interconnect technologies.
Generating SystemVerilog Assertion (SVA) Properties with Property Assist

Webinar - Jul 16, 2025 by Mark Eslinger

In this webinar, you will learn how Questa Property Assist automatically generates SystemVerilog Assertions (SVA) that describe the behavior of hardware designs, using AI technology. In addition, Property Assist turns user prompts into optimized LLM prompts, retrieves LLM provided solutions, and presents the best generated SVA solutions for the user.
Generating SystemVerilog Assertion (SVA) Properties with Property Assist

Resource (Slides (.PDF)) - Jul 16, 2025 by Mark Eslinger

In this webinar, you will learn how Questa Property Assist automatically generates SystemVerilog Assertions (SVA) that describe the behavior of hardware designs, using AI technology.
Aerospace & Defense

Reference - Jul 01, 2025 by

Welcome to the Aerospace and Defense event archive, where you will find presentations and slide decks from live events that you may have missed. *Please note: you will need a valid login to download the session presentations.
Smart Verification for Modern Complexity

Conference - Jun 23, 2025 by Abhi Kolpekwar

In this session, you will learn how scalable, intelligent verification strategies are addressing these modern complexity challenges through connected workflows, AI-enhanced automation, and data-driven insights.
Accelerating Functional Coverage with Questa One CX

Webinar - Jun 18, 2025 by Chris Crile

This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows.