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Introduction to SystemC & TLM-2.0

Session - Oct 27, 2011 by John Stickley

In this session, we provide an introduction of virtual prototyping and why co-emulation is so attractive for SoC verification.
SystemC & TLM-2.0 Testbench Modeling

Session - Oct 27, 2011 by John Stickley

In this session, we will talk about the advantages of using SystemC and OSCI TLM-2.0 standard for testbench modeling. The high level of abstraction of SystemC in conjunction with TLM-2.0 makes it perfect for virtual prototyping with co-emulation. A case study will be used to illustrate the process of implementing an accelerated verification environment.
The SCE-MI 2.0 Standard

Session - Oct 27, 2011 by John Stickley

In this session, we will talk about the SCE-MI 2.0 standard in the context of how it can be used with emulation. In particular this session describes how SCE-MI is very compatible subset of SystemVerilog 1800 DPI standard, and why it is so relevant for co-emulation.
The OSCI TLM-2.0 Standard

Session - Oct 27, 2011 by John Stickley

In this session, we will talk about the OSCI SystemC TLM-2.0 standard specifically in the context of how it can be used with emulation. Key areas include loosely-timed modeling, transport interfaces that are capable of transporting transactions and reusable transactions called generic payload.
Modeling SystemC TLM-2.0 Drivers

Session - Oct 27, 2011 by John Stickley

In this session, we will talk in detail about how to model TLM-2.0 compliant drivers and acceleratable transactors. A case study will be used to show how to implement transactors for a Wishbone Bus protocol.
SystemC & TLM-2.0 Monitors and Talkers

Session - Oct 27, 2011 by John Stickley

In this session, we will talk in detail about how to model TLM-2.0 compliant transactors. In this particular, we discuss the architecture of passive bus monitors and their associated acceleratable transactors. The Wishbone Bus protocol will be used to show how to implement monitor transactors.
Assertions for FPGA Designers

Resource (Slides (.PDF)) - Aug 23, 2011 by Cliff Cummings

In this session, you will learn about SystemVerilog Assertions by Cliff Cummings from Sunbust Design.
Advanced Debug with Questa

Resource (Slides (.PDF)) - Aug 01, 2011 by
Verification Horizons - Volume 7, Issue 2

Resource (Verification Horizons Archive) - Jun 01, 2011 by Tom Fitzpatrick

"As a special treat in this issue, we next introduce you to the Online UVM/OVM Methodology Cookbook.”
Transforming Verification and Verification Management

Webinar - Apr 08, 2011 by Tom Fitzpatrick

This session leads-off where all successful verification projects begin: verification planning and management. This includes verification plan creation, real-time tracking of progress against the plan, and analyzing results and trends throughout the project.
Power Aware Verification and UPF Tricks

Webinar - Apr 08, 2011 by Tom Fitzpatrick

In this session, you will learn how to apply low power design techniques with UPF to augment an existing flow for RTL and netlist.
Are OVM & UVM Macros Evil? A Cost-Benefit Analysis

Resource (Paper (.PDF)) - Mar 08, 2011 by Adam Erickson

Are macros evil? Well, yes and no. Macros are an unavoidable and integral part of any piece of software, and the Open Verification Methodology (OVM) and Universal Verification Methodology (UVM) libraries are no exception. Macros should be employed sparingly to ease repetitive typing of small bits of code, to hide implementation differences or limitations among the vendors’ simulators, or to ensure correct operation of critical features.
CDC Verification

Track - Feb 25, 2011 by Harry Foster

This track introduces a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics.
Overview and Welcome

Session - Feb 25, 2011 by Harry Foster

This session will cover the expectations that a user may experience after completing the Clock-Domain Crossing (CDC) Verification track.
Introduction to CDC

Session - Feb 25, 2011 by Harry Foster

This session introduces a survey of today’s CDC verification challenges, and the steps necessary to mature an organization’s CDC capabilities.
Understanding Metastability

Session - Feb 25, 2011 by Harry Foster

This session defines metastability and then discusses various techniques to address and verify the metastability problem.
Metastability Verification Flow

Session - Feb 25, 2011 by Harry Foster

This session introduces the three elements of a comprehensive CDC verification flow and then discusses how to scale a CDC flow to a full chip solution.
Modeling Metastability

Session - Feb 25, 2011 by Harry Foster

This session reviews the reconvergence problem and then introduces various home-grown methods to model metastability before discussing a comprehensive solution to modeling metastability.
Integrating CDC into a Flow

Session - Feb 25, 2011 by Harry Foster

This session introduces a systematic set of steps to help you integrate Clock-Domain Crossing (CDC) into your flow.
H/W-Assisted Testbench Acceleration

Session - Feb 25, 2011 by Dr. Hans van der Schoot

This session provides an introduction of hardware-assisted testbench acceleration.
Testbench Acceleration Depicted

Session - Feb 25, 2011 by Dr. Hans van der Schoot

This session provides a description of the considerations and recommended architecture utilized for acceleration of SystemVerilog testbenches with co-emulation. This includes a definition of how SystemVerilog testbench code (HVL) and design code (HDL) are partitioned.
Modeling for Acceleration

Session - Feb 25, 2011 by Dr. Hans van der Schoot

This session introduces the basic requirements of a standards-based co-emulation solution. It provides a technical description of the transaction-based communication mechanism between simulator and emulator.
Testbench Acceleration Flow

Session - Feb 25, 2011 by Dr. Hans van der Schoot

This session provides the recommended flow for rapid bring up of an accelerated testbench environment that can be used for both pure simulation and for hardware-assisted acceleration of SystemVerilog testbenches.
Why Plan?

Session - Feb 25, 2011 by Peet James

This session moves beyond general fear-based justifications for increased verification efforts to logical reasons for why verification typically is more overall effort than the actual design. This session uses gathered metrics to guide verification improvements, such as suggesting a verification progression to aide in better scheduling and implementation. This discussion spells out the argument for strategically planning verification, and for planning it early.
Why It's Hard

Session - Feb 25, 2011 by Peet James

This session covers seven historical reasons as to why the overall verification effort and verification planning in general is difficult.