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FPGA Verification Capabilities

Track - Aug 30, 2012 by Ray Salemi

This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
Introduction from Harry Foster

Session - Aug 30, 2012 by Harry Foster

This session is an introduction to various code coverage metrics and how to apply them.
Overview and Welcome

Session - Aug 30, 2012 by Ray Salemi

This session is an introduction to the seven steps for evolving your FPGA verification capabilities.
Code Coverage

Session - Aug 30, 2012 by Ray Salemi

This session is an introduction to various code coverage metrics and how to apply them.
Test Planning

Session - Aug 30, 2012 by Ray Salemi

This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
Applied Assertions

Session - Aug 30, 2012 by Ray Salemi

This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
Transactions

Session - Aug 30, 2012 by Ray Salemi

This session shows you how to create a transaction level test bench using modules instead of object.
Self-Checking Testbenches

Session - Aug 30, 2012 by Ray Salemi

This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
Automatic Stimulus

Session - Aug 30, 2012 by Ray Salemi

This session introduces constrained-random stimulus for automatic stimulus generation.
Functional Coverage

Session - Aug 30, 2012 by Ray Salemi

This session shows you how to implement functional coverage using SystemVerilog covergroups.
Using the UVM Register Layer

Resource (Slides (.PDF)) - Jun 22, 2012 by John Aynsley

Slides from DAC 2012 where John Anysley from Doulos shares the Architecture of the Register Layer, The Register Model and Running Register Sequences.
Siemens EDA has Accellera's Latest Standard Covered

Article - Jun 15, 2012 by Darron May

If you can't measure something, you can't improve it. For years, verification engineers have used "coverage" as a way to measure completeness of the verification effort. Of course, there are many types of coverage, from different types of code coverage to functional coverage, as well as many tools, both dynamic and static, that provide coverage information.
Is Intelligent Testbench Automation For You?

Article - Jun 15, 2012 by Mark Olen

Intelligent Testbench Automation (iTBA) is being successfully adopted by more verification teams every day. There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods. Technical conferences including DAC, DVCon, and others have joined those interested in better understanding this new technology.
Automated Generation of Functional Coverage Metrics for Input Stimulus

Article - Jun 15, 2012 by Mike Andrews - Siemens EDA

Questa inFact allows for graphical definition of the coverage goals and can, with the 10.1 release, automatically generate SystemVerilog covergroups from this definition, including the exclusions needed to accurately represent the achievable coverage. This article describes how this capability can simplify the definition of more comprehensive stimulus coverage metrics.
On the Fly Reset

Article - Jun 15, 2012 by Mark Peryer

A common verification requirement is to reset a design part of the way through a simulation to check that it will come out of reset correctly and that any non-volatile settings survive the process. Almost all testbenches are designed to go through some form of reset and initialization process at their beginning, but applying reset at a mid-point in the simulation can be problematic.
Relieving the Parameterized Coverage Headache

Article - Jun 15, 2012 by Byran Ramirez

Modern FPGA and ASIC verification environments use coverage metrics to help determine how thorough the verification effort has been. Practices for creating, collecting, merging and analyzing this coverage data is documented for designs operating in a single configuration. However, complications arise when parameters are introduced into the design, especially when creating customizable IP. This article discusses the coverage-related pitfalls and solutions when dealing with parameterized designs.
Better Living Through Better Class-Based SystemVerilog Debug

Article - Jun 15, 2012 by Rich Edelman

SystemVerilog 1 UVM 2 class-based testbenches have become as complex as the hardware under test, and are evolving into large object-oriented software designs. The usual RTL debugging techniques must be updated to match this new complexity. Debugging tools are addressing these complexities, but this article will describe techniques and approaches that can be used to help debug these complex environments without advanced debug tools.
Introduction to Metrics

Session - Jun 01, 2012 by Harry Foster

This session provides an introduction and motivation for introducing metrics-driven processes into your flow.
The Driving Forces for Change

Session - Jun 01, 2012 by Andreas Meyer

This session examines the issues that are motivating change and the need for metrics-driven processes.
What Can Metrics Tell Us?

Session - Jun 01, 2012 by Andreas Meyer

This session expand our discussion on what metrics can tell us by providing examples for various common processes within today’s SoC verification flow.
What's Needed to Address the Problem?

Session - Jun 01, 2012 by Andreas Meyer

This session discusses four important aspects of a successful metrics-driven process.
What's Needed to Adopt Metrics?

Session - Jun 01, 2012 by Andreas Meyer

This session discusses important aspects of an implementation that should be considered when architecting a solution.
Evolving Trends in Functional Verification

Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster

2012 Wilson Research Group Functional Verification Study Results
What to Expect After Adopting the Metrics

Session - Jun 01, 2012 by Andreas Meyer

This session provides a conclusion of what benefits to expect after you adopt metrics-driven processes.
Metrics in SoC Verification

Track - Jun 01, 2012 by Andreas Meyer

In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.

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Track - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Harry Foster

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Session - Aug 30, 2012 by Ray Salemi

Resource (Slides (.PDF)) - Jun 22, 2012 by John Aynsley

Article - Jun 15, 2012 by Darron May

Article - Jun 15, 2012 by Mark Olen

Article - Jun 15, 2012 by Mike Andrews - Siemens EDA

Article - Jun 15, 2012 by Mark Peryer

Article - Jun 15, 2012 by Byran Ramirez

Article - Jun 15, 2012 by Rich Edelman

Session - Jun 01, 2012 by Harry Foster

Session - Jun 01, 2012 by Andreas Meyer

Session - Jun 01, 2012 by Andreas Meyer

Session - Jun 01, 2012 by Andreas Meyer

Session - Jun 01, 2012 by Andreas Meyer

Resource (Slides (.PDF)) - Jun 01, 2012 by Harry Foster

Session - Jun 01, 2012 by Andreas Meyer

Track - Jun 01, 2012 by Andreas Meyer