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Verification IP Stimulus APIs - Are They Really Easy to Use?

Paper - Dec 01, 2015 by Amit Kumar Jain - Siemens EDA

With the increasing complexity of system designs, there is a pressing need for standalone, pre-verified, built-in verification infrastructures. Verification IP (VIP) is an integral and important component of these infrastructures for block and system-level verification as they reduce cycles spent in verifying complex designs.ly Easy to Use?
Verification IP Stimulus APIs - Are They Really Easy to Use?

Resource (Paper (.PDF)) - Dec 01, 2015 by Amit Kumar Jain - Siemens EDA

Stimulus generation is an important aspect of verification for creating both simple and complex scenarios used to hit functional bugs in a design. Stimulus generation application program interfaces (API) in VIP help you write stimulus without much protocol knowledge and help them create complex protocol scenarios for testing.
Patterns Library

Pattern - Dec 01, 2015 by Harry Foster

The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
Leveraging Verification IP (VIP) for Fast & Efficient Verification

Resource (Slides (.PDF)) - Nov 25, 2015 by Jason Polychronopoulos

In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.
UVM Framework – Create a UVM Environment in Less than an Hour

Webinar - Nov 25, 2015 by Bob Oden

In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.
Leveraging Verification IP (VIP) for Fast & Efficient Verification

Webinar - Nov 25, 2015 by Jason Polychronopoulos

In this session you will learn how Verification IP (VIP) helps to overcome IP verification challenges.
UVM Framework – Create a UVM Environment in Less than an Hour

Resource (Slides (.PDF)) - Nov 25, 2015 by Bob Oden

In this session you will learn how the UVM Framework delivers reuse from block to chip to system in simulation and emulation and how to reduce your verification schedule by at least four weeks on every project.
Technical Paper: A New Stimulus Model for CPU Instruction Sets

Resource - Nov 24, 2015 by
UVM Forum - All Slides

Resource (Slides (.PDF)) - Nov 24, 2015 by
UVM Forum Seminar - 2015: UVM Enabled Advanced Storage IP Silicon Success

Resource - Nov 24, 2015 by
UVM and Emulation - Easing the Path to Advanced Verification and Analysi

Resource (Slides (.PDF)) - Nov 24, 2015 by Sanjay Gupta
Automating Scenario-Level UVM Tests with Portable Stimulus

Resource (Slides (.PDF)) - Nov 24, 2015 by Matthew Ballance

In this session, you will learn how to easily leverage lower-level descriptions, such as sequence items, in larger scenarios and efficiently and predictably exercise the scenario space, ensuring high quality verification results.
UVM Forum Seminar - 2015: Improving UVM Testbench Debug Productivity and Visibility

Resource - Nov 24, 2015 by
Creating UVM Testbenches for Simulation & Emulation Platform Portability

Resource (Slides (.PDF)) - Nov 24, 2015 by Hans Van Der Schoot

In this session, you will learn the fundamentals of hardware-assisted testbench acceleration.
UVM Forum Seminar - 2015: UVM Technology Overview

Resource - Nov 24, 2015 by
UVM Forum Seminar - 2015: UVM Everywhere: Industry Drivers, Best Practices, and Solutions

Resource - Nov 24, 2015 by
ISO 26262 Fault Analysis – Worst Case is Really the Worst

Article - Nov 10, 2015 by Avidan Efody

Imagine you’re a verification engineer being asked to get a small 10K gate design ISO 26262 certified. Assuming you don’t take the smart decision to quit your job, what would be your first step? If you would have been asked to do plain functional verification of the design, it is obvious you would start by reading the DUT spec.
Memories Are Made Like This

Article - Nov 01, 2015 by Mark Peryer

One of the most common requirements for the verification of a chip, board or system is to be able to model the behavior of memory components, and this is why memory models are one of the most prevalent types of Verification IP (VIP).
A New Stimulus Model for CPU Instruction Sets

Article - Nov 01, 2015 by Staffan Berg, Mike Andrews - Siemens EDA

Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and micro-architectural feature has been exercised. Typical approaches involve collecting large test-suites of real SW, as well as using program generators based on constrained- random generation of instruction streams, but there are drawbacks to each.
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk

Article - Nov 01, 2015 by Eric Rentschler - Siemens EDA

With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions.
Hardware Emulation: Three Decades of Evolution - Part III

Article - Nov 01, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

At the beginning of the third decade, circa 2005, system and chip engineers were developing evermore complex designs that mixed many interconnected blocks, embedded multicore processors, digital signal processors (DSPs) and a plethora of peripherals, supported by large memories. The combination of all of these components gave real meaning to the designation system on chip (SoC).
QVIP Provides Thoroughness in Verification

Article - Nov 01, 2015 by Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd.

The present day designs use standard interfaces for the connection and management of functional blocks in System on Chips (SoCs). These interface protocols are so complex that, creating in-house VIPs could take a lot of engineer’s development time. A fully verified interface should include all the complex protocol compliance checking, generation and application of different test case scenarios, etc.
Minimizing Constraints to Debug Vacuous Proofs

Article - Nov 01, 2015 by Anshul Jain - Oski Technology

Most false positives (i.e. missing design bugs) during the practice of model checking on industrial designs can be reduced to the problem of a failing cover. Debugging the root cause of such a failing cover can be a laborious process, when the formal testbench has many constraints. This article describes a solution to minimize the number of model checking runs to isolate a minimal set of constraints necessary for the failure. This helps improve formal verification productivity.
A Generic UVM Scoreboard

Article - Nov 01, 2015 by Jacob Andersen, Kevin Seffensen, Peter Jensen - SyoSil ApS

All UVM engineers employ scoreboarding for checking DUT/reference model behavior, but only few spend their time wisely by employing an existing scoreboard architecture. The main reason is that existing frameworks have inadequately served user needs and have failed to improve user effectiveness in the debug situation. This article presents a better UVM scoreboard framework, focusing on scalability, architectural separation and connectivity to foreign environments.
Getting ISO 26262 Faults Straight

Resource (Verification Horizons Blog) - Oct 26, 2015 by Avidan Efody

Random hardware faults – i.e. individual gates going nuts and driving a value they’re not supposed to – are practically expected in every electronic device, at a very low probability. When we talk about mobile or home entertainment devices, we could live with their impact. But when we talk about safety critical designs, such as automotive or medical, we could well die from it. That explains why ISO 26262 automotive safety standard is obsessed with analyzing and minimizing the risk they pose.