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PSS (28)
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Classes (27)
Introduction to UVM (27)
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Scoreboard (26)
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VHDL (26)
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Objects (24)
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UVM Basics (24)
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Cookbook (23)
Metastability (23)
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Waveform (22)
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Design Constructs (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
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State Space (17)
U2U Europe (17)
Coverage Points (16)
Covergroup (16)
DFT (16)
Packages (16)
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Sequence Driver (16)
Signal (16)
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Inconclusives (15)
Netlist (15)
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ABV (14)
Automotive Functional Safety Forum (14)
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Driver (14)
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Gate-Level (14)
March 2016 - Volume 12 Issue 1 (14)
Performance (14)
Report (14)
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Testplan (14)
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VRM (14)
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BFMs (13)
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Sequencer (13)
Variable (13)
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Arrays (12)
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HLS (12)
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September 2021 - Volume 17 Issue 2 (12)
Unit Testing (12)
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Verification IQ (12)
Verification Run Manager (12)
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Aerospace and Defense Verification Tech Day (11)
C (11)
Creating and Using Constrained Random (11)
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Generation (11)
Interview (11)
Jenkins (11)
June 2015 - Volume 11 Issue 2 (11)
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Methods (11)
NVMe (11)
PYUVM (11)
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Processor Design Verification (11)
Productivity Gap (11)
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Register Layer Adapter (11)
Tool Assessment (11)
Verification Process Overview (11)
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Continuous Integration System (10)
Coverage Models (10)
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Inheritance (10)
Interrupts (10)
July 2022 - Volume 18 Issue 2 (10)
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Memory Models (10)
OVM (10)
Operators (10)
Proof Coverage (10)
Property Debug (10)
Root of Trust (10)
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Stimulus Generation (10)
Unified Power Format (10)
VIQ (10)
Analog (9)
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Creating and Using Functional Coverage (9)
Curriculum (9)
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Data Types and Procedural Statements (9)
Deadlock (9)
Declaration (9)
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June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
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Reset Architecture (9)
Sequence-Driver Use Models (9)
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Whats New in Functional Verification (9)
1800.2 (8)
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Checkers (8)
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HTML Docs (8)
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Matlab (8)
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Supply Set (8)
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VHDL-2008 (8)
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3DIC (7)
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AXI (7)
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Chiplets (7)
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Convergence (7)
DAC 2019 (7)
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Execution Semantics and Synchronization (7)
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Gate-Level Simulation (7)
IP Blocks (7)
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ISA (7)
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Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
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March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Metastable (7)
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Order Property Pattern (7)
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Traceability (7)
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Waivers (7)
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Design Integrity (6)
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Distributed Resource Management (6)
Electronic Hardware (6)
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HDL Domain (6)
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June 2019 - Volume 15 Issue 2 (6)
LLMs (6)
MARLUG 2023 (6)
MBIST (6)
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March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Multi-Core Architectures (6)
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Open Source (6)
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SPI (6)
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VA Live 2024 - El Segundo (6)
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Verbosity (6)
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Voltage Domain Crossing (6)
Windows (6)
X-Effects (6)
YAML (6)
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ATPG (5)
Advance Your Verification Methodology (5)
Analysis Pattern (5)
BIST (5)
Backdoor Accesses (5)
Co-Simulation (5)
Command API (5)
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Creating and Using a Test Plan (5)
DAC 2018 (5)
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DSP (5)
Data Transfer (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Scaling (5)
Digital Design (5)
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Error (5)
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FMEDA (5)
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February 2019 - Volume 15 Issue 1 (5)
Flip-Flop (5)
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Functional Correctness (5)
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HBM4 (5)
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High-Level Synthesis (5)
JEDEC (5)
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Low Power Verification Forum (5)
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March 2018 - Volume 14 Issue 1 (5)
Mixed-Signal Design (5)
Non-Determinism (5)
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PSL (5)
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SVUnit (5)
Simulink (5)
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Sub-system Level (5)
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VA Live 2019 - Westford (5)
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November 2018 - Volume 14 Issue 3 (4)
Objections (4)
PCIe Gen 6 (4)
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UART (4)
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1.2 (3)
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July 2023 - Volume 19 Issue 2 (3)
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OSCI (3)
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June 2014 - Volume 10 Issue 2 (2)
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