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Adding Tests and Sequences
Session - Apr 12, 2018 by Bob Oden
In this session, you will learn how to add sequences and test cases to a UVMF testbench using the example derived test and extended top level virtual sequence. You will also learn how to specify tests and sequences from the command line.
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Instantiating the DUT
Session - Apr 12, 2018 by Bob Oden
In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench. You will also learn how to connect bus functional models to primary DUT ports as well as internal DUT interfaces.
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Instantiating the DUT
Resource (Slides (.PDF)) - Apr 12, 2018 by Bob Oden
In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench.
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Bench Code Generation
Session - Apr 12, 2018 by Jonathan Craft
In this session, you will learn the format and content of the YAML configuration file that describe the UVMF bench and what parts of the generated output that you’ll need to modify afterwards.
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Bench Code Generation
Resource (Slides (.PDF)) - Apr 12, 2018 by Jonathan Craft
In this session, you will learn the format and content of the YAML configuration file that describe the UVMF bench.
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Probe Class
Resource (Reference Documentation) - Apr 01, 2018 by Dave Rich
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Scoreboards
Chapter - Mar 31, 2018 by Verification Methodology Team
The Scoreboard's job is to determine whether or not the DUT is functioning properly.
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Pipelined Protocols
Chapter - Mar 31, 2018 by Verification Methodology Team
In a pipelined bus protocol a data transfer is broken down into two or more phases which are executed one after the other, often using different groups of signals on the bus
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UVM Components
Chapter - Mar 27, 2018 by Verification Methodology Team
UVM testbench is composed of component objects extended from the uvm_component base class.
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How Formal Reduces Fault Analysis for ISO 26262
Conference - Mar 27, 2018 by Doug Smith
In this session, you will learn how Formal reduces fault analysis for ISO 26262 with advanced techniques that eliminate large numbers of irrelevant faults without compromising the completeness of the verification, or the safety of the finished product.
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Requirement Tracing in the ISO 26262 World
Webinar - Mar 27, 2018 by Charles Battikha
In this session, you will learn about requirement tracing in ISO 26262 and the basics of the ISO 26262 standard as it applies to requirements for electronic design & verification of safety critical products.
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ISO 26262: Compliant Verification From Analysis to Fault Campaigns
Conference - Mar 27, 2018 by Doug Smith
In this session, you will gain an understanding of the core mission, scope, and key concepts of ISO 26262 for automotive functional safety, analysis, and fault campaigns.
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Block Level Testbench
Chapter - Mar 24, 2018 by VM Team
As an example of a block level testbench, consider a testbench built to verify a SPI Master DUT. In this case, the UVM environment has two agents - an APB agent to handle bus transfers on its APB slave port, and a SPI agent to handle SPI protocol transfers on its SPI port. The structure of the overall UVM verification environment is illustrated in the block diagram. Let us go through each layer of the testbench and describe how it is put together from the top down.
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Integration Level Testbench
Chapter - Mar 23, 2018 by VM Team
This testbench example is one that takes two block level verification environments and shows how they can be reused at a higher level of integration. The principles that are illustrated in the example are applicable to repeated rounds of vertical reuse.
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Testbench Architecture
Chapter - Mar 21, 2018 by VM Team
This chapter covers the basics and details of UVM testbench architecture, construction, and leads into other chapters covering each of the constituent parts of a typical UVM testbench. A UVM testbench is built using SystemVerilog (dynamic) class objects interacting with SystemVerilog (static) interfaces and modules in a structured hierarchy. The hierarchy is composed of layers of functionality. At the center of the testbench is the Design Under Test (DUT).
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Specifying Registers
Chapter - Mar 18, 2018 by Verification Methodology Team
Hardware functional blocks connected to host processors are managed via memory mapped registers.
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Register-Level Functional Coverage
Chapter - Mar 18, 2018 by Verification Methodology Team
The UVM supports the collection of functional coverage based on register state in three ways:
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Testbench Basics
Chapter - Mar 15, 2018 by Verification Methodology Team
Before we can get into discussing the recipes presented in the UVM Cookbook, we have to make sure that we're all talking about the same ingredients. This chapter introduces the UVM concepts that the reader should know in order to understand the recipes presented herein. This section will be incredibly valuable to new UVM users, but experienced UVM users may be able to just straight to the UVM Testbench chapter.
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Interfaces and Virtual Interfaces
Chapter - Mar 15, 2018 by VM Team
The SystemVerilog interface provides a convenient means of organizing related signals into a container in order to simplify connections between modules. An interface may be declared with or without ports. If it is declared with ports, then those ports need to be assigned to signals when the interface is instantiated.
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UVM
Cookbook - Mar 15, 2018 by Verification Methodology Team
The (2018) version conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond. Find all the UVM methodology advice you need in this comprehensive and vast collection.
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UVM Cookbook
Resource (Cookbook) - Mar 15, 2018 by Verification Methodology Team
The UVM Cookbook conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond.
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UVM Sequences
Chapter - Mar 15, 2018 by VM Team
In testbenches written in traditional HDLs like Verilog and VHDL, stimulus is generated by layers of sub-routine calls which either execute time consuming methods (i.e. Verilog tasks or VHDL processes or procedures) or call non-time consuming methods (i.e. functions) to manipulate or generate data.
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UVM Configuration Database
Chapter - Mar 15, 2018 by VM Team
The uvm_config_db is a UVM utility class that is used to pass configuration data objects between component objects in a UVM testbench. Any call to the uvm_config_db is parameterized with the type of the data object that is stored or retrieved. To store an object in the uvm_config_db, its set() method is used, and to retrieve an object from the uvm_config_db, its get() method is used.
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Handling Parameterization
Chapter - Mar 15, 2018 by VM Team
Parameters are commonly used to configure design IP and interfaces. From the perspective of VIP, parameters usually affect the width of bus fields or the number of channels or lanes in use. SystemVerilog interfaces may be parameterized and, when they are, their virtual interface handles also need to be parameterized.
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Virtual Interface BFMs
Chapter - Mar 15, 2018 by VM Team
In order to make verification components reusable between testbenches they are organized as uvm_agents with an associated signal interface. These are also referred to as UVCs (Universal Verification Components). Inside the uvm_agent, there are two types of uvm_components that interact with the virtual interface.